Accurate circuit performance prediction model and lifetime prediction method of nbt stressed devices for highly reliable ulsi circuits

Accurate negative bias temperature instability lifetime prediction based on hole injection

“…Additionally, the grounded n-well guarantees that the injected holes are not given any energy while diffusing from backside p + substrate to the end of the depletion layer of the stressed device, thus only the rate of the degradation is accelerated by increased number of holes, but not energy of holes. Hole injection method has its limit in allowable injection amount [29][30][31][32][33]. With the appropriate region, we can obtain the quantitative NBTI degradation behavior with no acceleration of the gate voltage and the temperature.…”

“…Fig. 2a and b shows the schematic view and the energy band diagram during the stressing period of the hole injection method [29][30][31][32][33]36], respectively. The acceleration parameter is defined by the gate current density (J inj ) which is proportional to the amount of the non-energetic cold holes injected into the inversion layer during the stress [31].…”

“…This result indicates that the dominant degradation mechanism is changed in these acceleration conditions from that of the operation condition. Thus, to develop the degradation model for the lifetime prediction and the circuit performance prediction, we must only use the degradation behavior of devices stressed by hole injection method in the low J inj regime with operation bias and temperature condition among the experimented degradation acceleration methods [29][30][31][32][33]. Then, the hole acceleration method is applied to these PMOSFETs with SiO 2 and SiON films instead of the conventional stress condition such as high gate voltage stress.…”

“…The gate currents with and without the hole injection are required to calculate J inj . The gate current is measured by a conventional carrier separation technique [29][30][31][32][33]37,38]. The carrier separation measurement is executed while the drain/source and well are biased at common.…”

“…Compared to the operation condition of 4-8 MV/cm and <398 K, measurement bias and temperature acceleration induces much larger degradation to p-MOSFETs' electrical characteristics than that occurs in the LSI operation condition and makes the lifetime-prediction difficult. We have reported that the degradation mechanism is different between the operation condition and the high stress conditions which are often used for NBTI lifetime measurement [29][30][31][32][33]. The high gate voltage not only increases the hole density in the inversion layer but also causes an excessive band bending, as a result, the band bending enhances the hole energy.…”