Accurate device simulations through CD-SEM-based edge-contour extraction

Abstract

A new methodology to predict changes in device performances due to systematic lithography and etch effects is described in this paper. Our methodology consists on Automatic Edge-Contour-Extraction (ECE) on Poly Over Active Layer, taking along the manufacturing variability. In general, the AMAT SEM (Scanning Electron Microscopy) ECE algorithm is based on CAD (GDS) to SEM pattern recognition, followed by CD based 2D edge extraction. Device modeling (using SPICE simulation) is used, to predict the nominal values as well as the device performances variability of the transistors drive current (Ion) and leakage current (Ioff). We used our method to compare a classical (simple rectangular) transistors and "UShape AA" transistors, both manufactured using Tower TS013LL (0.13um Low-Leakage) Platform. It was found, as predicted, that U-shape transistors have larger W distribution. However, "U-shape" also showed much tighter L distribution and the overall Ion spread is lower comparing to classical transistors. Also, UShape transistors found to have lower Lstdev (gate length distribution of each individual transistor). We also used the ECE methodology, to compare transistors of single side dog-bone to double-side dog-bone. Based on our work, we can predict that single-side dog-bone transistors, will have higher and larger Ioff distributions, and the overall Ioff speared along the wafer, will go up to a factor of x2.5.

Process monitoring using automatic physical measurement based on electrical and physical variability analysis

“…6 We focused on accurate extraction of statistical physical information from transistors having a gate definition only [without any well or source/drain (S/D) implants]. 6. Data extracted from wafers just after the M1 single-Damascene Cu etch but before the Cu fill in a stage when only the CS (contact) area that will be overlapped by the M1 was seen.…”

“…Therefore, Fig. 6 they are built on a paradigm of "Edge," and include edge detection as a principle algorithmic component. 3 Fig.…”

“…Transistor and Dense Transistor and the Effect of Dummies 6 We start with a simple, "classic" example, a comparison the physical and electrical performances of two transistor types, both having transistor width and length of 0.3 μm and 0.13 μm, respectively (Fig. 4).…”

“…DUT8 shows better (lower) LWR all across the wafer 6. (a) Schematic layout and the layout parameters.…”

CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

“…I sub was calculated based on L min , σ L and W avg were L min and σ L are the minimum gate length and the related standard deviation of every transistor. More details on this calculation method are given in [15]. The I on /I sub characteristic was used, in order to compare the performance of different transistor configurations.…”