Accurate new scaling routines for any table/function based FET model including temperature and noise behaviour

Follmann, Rüdiger; Tempel, R.; Herrmann, Johannes M.; Sporkmann, T.; Wolff, I.

doi:10.1109/euma.1998.338132

Cited by 3 publications

(3 citation statements)

References 3 publications

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“…In Figure 10, the measurement of the fifth harmonic can be seen together with the simulation of the circuit using a Curtice cubic model [9] and the TOPAS [1,6,7] model using the calculation theory described previously. As can be seen, the simulation using the TOPAS model is in good agreement to measurement, whereby the Curtice model has some seriously convergence problems in the power range between -5 and +5 dBm input power.…”

Section: Verificationsmentioning

confidence: 99%

“…Our approach [6], [7] measures and extracts the devices out of a matrix of transistors with varying numbers of gate fingers and different gate finger widths. From the scaling calculation, we take a cross of devices consisting of one line with constant number N of gate fingers and another line of constant gate finger width W t .…”

Section: Scaling Temperature and Noisementioning

confidence: 99%

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Extraction and modeling methods for FET devices

et al. 2000

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T here are many ways of modeling field effect transistor (FET) devices. Physics-based models do not require any kind of measurements. They are completely based on the physics of the FET and simulate its behavior solving semiconductor equations for different geometries and doping profiles. Although these models are very flexible, they are (to date) not useful to circuit design engineers because of their huge amount of computing time. The most common way in modeling FETs is the use of an equivalent circuit. The elements of the circuit are extracted using different kinds of measurements and afterwards described using either mathematical equations or look up tables. Both equations and tables must allow interpolation between nonmeasured DC values.This article describes an efficient method for FET modeling that requires a minimum number of measurements, namely only a set of small signal scattering parameters at different bias points. The proposed method is based on spline functions, takes into account thermal and noise effects, allows a scaling of different FET device geometries, and is available in commercial CAD software like Agilents Series IV or ADS. Equivalent CircuitsThe equivalent circuit of a FET can be divided into two parts: constant and bias independent extrinsic elements and a bias dependent intrinsic part. Each element has a physical meaning. The extrinsic elements, for example, describe pad capacitances or resistivity of the transistor lines whereby the intrinsic charge zone of the FET is represented by the gate-source and gate-drain capacitances ( Figure 1).We propose an equivalent circuit [1] based on the well known 15 element circuitry [2], [3]. Some changes (Figure 1), however, are required for the nonlinear modeling:q All intrinsic elements are extracted bias dependent (both voltages) q The current source I DS is replaced by measured IV-curves I DS (V GS , V DS ) q Two Schottky diodes, which can be determined from the measured scattering parameters, describe its compression behavior September 2000 49

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Section: Verificationsmentioning

confidence: 99%

Section: Scaling Temperature and Noisementioning

confidence: 99%

Extraction and modeling methods for FET devices

et al. 2000

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“…This program provides a library of several elements, such as junctions, coils, and capacitors, which are calculated quasi-statically. Additionally, the library includes different models, such as the Curtice or the TOPAS model for the simulation of transistors [13]. Those models simulate the transistor chip, but they do not take into consideration-unlike the circuits in the hybrid technique-either housing structures or bond connections.…”

Section: Monolithic Integrated Mixersmentioning

confidence: 99%