Accurate prediction of PQFP warpage

Kelly, G.; Lyden, C.; Lawton, W.; Barrett, J.; Saboui, A.; Exposito, J.; Lamourelle, F.

doi:10.1109/ectc.1994.367644

Cited by 36 publications

(12 citation statements)

References 9 publications

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“…Such relationships have also been reported in other studies [3,4,5,6]. For the purpose of this study, commercially available die attach and molding compounds were selected that had a wide range of glass transition (Tg), coefficient of thermal expansion (CTE) above and below the Tg temperature, and elastic modulus (E) at low and high temperature.…”

Section: Evaluation Methodologymentioning

confidence: 89%

Controlling Top Package Warpage for POP Applications

Carson

Lee

Vijayaragavan³

2007

2007 Proceedings 57th Electronic Components and Technology Conference

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The need to integrate devices in the vertical dimension to reduce space, thickness, and cost for handheld applications has fueled enormous growth of what can be termed 3D packaging.Due to testability, business flow, and configuration flexibility issues, the Package on Package (POP) vertical stacking solution has emerged as the preferred method to stack mobile phone logic processor with memory. The POP solution typically consists of the logic processor in the bottom package and memory device stack in the top package. The bottom package has land pads on the top perimeter in order to allow top package to be mounted and reflowed above. Both packages must be capable of being placed on the PC Board and reflowed simultaneously to each other and to the board. Control of the top and bottom package warpage is a critical issue impacting board mount yields and adoption. A series of experiments were performed to determine the impact of different materials and construction on the warpage of the top package at reflow temperature. From this work certain trends are apparent and can be used to optimize the top package warpage to assure compatibility of warpage with the bottom POP and high yields during the simultaneous reflow of the POP stack to the motherboard. POP Warpage and Board MountThe POP module consists of a bottom package, with peripheral land pads on the top surface, to allow the mounting and interconnection of a top package, which has a corresponding peripheral solder ball array (see Figure 1). Electrical interconnection of the stacked packages is achieved by means of reflow of the top package solder balls to the lands on top of the bottom package. Electrical interconnection of the bottom package is achieved by means of reflow of the bottom package to the motherboard of the product application. A typical product application for POP today is for mobile phones. The bottom package typically houses the logic base band or application processor, while the top package contains the memory devices to compliment the processor and provide the advanced features and performance required for high and mid-tier mobile phones. To allow the most configuration flexibility to the handset maker, simultaneous reflow of the top package to the bottom package on the motherboard is desired (see Figure 2). This allows the handset maker to configure and match memory size and type with processor as needed to meet the needs of a particular phone for a particular market [1]. However, simultaneous reflow of the thin top and bottom package to the motherboard, which is itself thin and typically has components mounted on both sides, can be problematic due to temperature dependent warpage of the packages, the board, and the clearances involved [1,8]. Therefore, warpage of the POP during the reflow process needs to characterized, optimized, and controlled in order to achieve acceptable board mount yields. Top Package Figure 1: POP construction cocs4#ier Ared Gc) aliability EndGaer astad liaiXLity Figure 2: schematic of simultaneous reflow Due to the const...

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Section: Evaluation Methodologymentioning

confidence: 89%

Controlling Top Package Warpage for POP Applications

Carson

Lee

Vijayaragavan³

2007

2007 Proceedings 57th Electronic Components and Technology Conference

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“…11 Cross sectional view of EMC warping Fig. 9 Variation of Q-factor during high temperature storage test (85°C) after improvement and re-fabrication of another set of gyroscope chips (Kelly et al 1994). Shrinkage of EMC material used in this study is around 0.2% in linear dimension based on manufacturer's data.…”

Section: Packaging Induced Stressmentioning

confidence: 99%

Reliability of MEMS packaging: vacuum maintenance and packaging induced stress

Choa

2005

Microsyst Technol

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In this study, the dominant reliability issues of MEMS packaging that include vacuum maintenance and packaging induced stress, are discussed, and design considerations to improve the reliability are presented. The MEMS vibratory gyroscope sensor is fabricated with anodically bonded wafer level vacuum packaging followed by die-bonding and wire-bonding processes. The epoxy-molding compound (EMC) is applied to encapsulate the gyroscope sensor. Several methods to improve reliability of the vacuum packaging are suggested based on extensive work. The two major failure mechanisms of anodic vacuum packaging, namely leakage and outgassing are investigated. Leakage is effectively reduced by optimization of the bonding process. Outgassing inside the cavity can be minimized by application of Ti coating. Packaging induced stress is mainly caused by thermal expansion mismatch among the materials used to fabricate the package. During anodic bonding, thermo-mechanical stress is generated to the bonded wafer, which increases with temperature. The EMC encapsulation also produces package-induced stress. In order to increase robustness of the structure against deformation, a ''crab-leg'' type spring is replaced with a semi-folded spring. The results show that the frequency shift is greatly reduced after applying the semifolded spring.

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“…In general, different coefficients of thermal expansion (CTE) values between constitutive materials were considered as the main reasons for warpage [1] [2] [3]. In recent years, there are more evidences showing that it is not sufficient to predict the amount of warpage of IC packages if considering only the CTE value difference between constitutive materials [4] [5] [6] [10].…”

Section: Introductionmentioning

confidence: 99%

Warpage simulations with P-V-T-C equation and experiments of fan-out wafer level package after encapsulation process

Deng

Hwang

Lee

et al. 2010

2010 5th International Microsystems Packaging Assembly and Circuits Technology Conference

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Wafer level packaging is the technique that encapsulates integrated circuit on the wafer directly and different from the traditional IC package. Comparing with the traditional IC package, wafer level chip scale packaging has several advantages such as: smaller package size (reduce area and thickness), lighter weight, more fabricate simply, better electric performance and cost down. Therefore, the wafer level package is suitable for cell phones, notebooks, handheld computers and digital cameras. In addition, the wafer level package can integrate wafer manufacture, encapsulation and test that simplifies the all production processes. The fan-out wafer level package discussed here has the flip chip form which uses thin-film redistribute then uses solder bump to connect the package to the printed wiring board directly. Liquid compound was used for the encapsulation process. Because the thickness of the fan-out wafer level package is thinner than traditional IC package, so the fan-out wafer level package produced more serious warpage. Warpage plays an important role during integrated circuit encapsulation process and the too large amount of warpage will not proceed to the next manufacture process in this study. Previous researchers had focused on warpage analysis with thermal-induced shrinkage and the cure-induced shrinkage was neglected. However, more and more studies indicated that the prediction of warpage only according to CTE (Coefficient of Thermal Expansion) was not able to accurately predict the amount of warpage in IC packaging. This study used an approach considering both cureand thermal-induced shrinkage during encapsulation process was presented to predict the amount of warpage. The cureinduced shrinkage was described by the pressure-volumetemperature-cure (P-V-T-C) equation of the liquid compound. The thermal-induced shrinkage was described by the coefficients of thermal expansion of the component materials. The liquid compound properties were obtained by various techniques: cure kinetics by differential scanning calorimeter (DSC), cure induced shrinkage by P-V-T-C testing machine. These experimental data were used to formulate the P-V-T-C equation.In this study, fan-out wafer level package was used for the simulation. The simulation results were verified with experiments. It showed that the approach of considering both thermal and cure/compressibility effects could better predict the amount of warpage for fan-out wafer level package. The P-V-T-C equation was successfully implemented and verified that warpage was governed by both thermal shrinkage and cure shrinkage. The amount of warpage after molding could be accurately predicted with this methodology. The simulation results showed that cure shrinkage of liquid compound was the dominant factor for package warpage after encapsulation.

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Accurate prediction of PQFP warpage

Cited by 36 publications

References 9 publications

Controlling Top Package Warpage for POP Applications

Controlling Top Package Warpage for POP Applications

Reliability of MEMS packaging: vacuum maintenance and packaging induced stress

Warpage simulations with P-V-T-C equation and experiments of fan-out wafer level package after encapsulation process

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