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The need to integrate devices in the vertical dimension to reduce space, thickness, and cost for handheld applications has fueled enormous growth of what can be termed 3D packaging.Due to testability, business flow, and configuration flexibility issues, the Package on Package (POP) vertical stacking solution has emerged as the preferred method to stack mobile phone logic processor with memory. The POP solution typically consists of the logic processor in the bottom package and memory device stack in the top package. The bottom package has land pads on the top perimeter in order to allow top package to be mounted and reflowed above. Both packages must be capable of being placed on the PC Board and reflowed simultaneously to each other and to the board. Control of the top and bottom package warpage is a critical issue impacting board mount yields and adoption. A series of experiments were performed to determine the impact of different materials and construction on the warpage of the top package at reflow temperature. From this work certain trends are apparent and can be used to optimize the top package warpage to assure compatibility of warpage with the bottom POP and high yields during the simultaneous reflow of the POP stack to the motherboard. POP Warpage and Board MountThe POP module consists of a bottom package, with peripheral land pads on the top surface, to allow the mounting and interconnection of a top package, which has a corresponding peripheral solder ball array (see Figure 1). Electrical interconnection of the stacked packages is achieved by means of reflow of the top package solder balls to the lands on top of the bottom package. Electrical interconnection of the bottom package is achieved by means of reflow of the bottom package to the motherboard of the product application. A typical product application for POP today is for mobile phones. The bottom package typically houses the logic base band or application processor, while the top package contains the memory devices to compliment the processor and provide the advanced features and performance required for high and mid-tier mobile phones. To allow the most configuration flexibility to the handset maker, simultaneous reflow of the top package to the bottom package on the motherboard is desired (see Figure 2). This allows the handset maker to configure and match memory size and type with processor as needed to meet the needs of a particular phone for a particular market [1]. However, simultaneous reflow of the thin top and bottom package to the motherboard, which is itself thin and typically has components mounted on both sides, can be problematic due to temperature dependent warpage of the packages, the board, and the clearances involved [1,8]. Therefore, warpage of the POP during the reflow process needs to characterized, optimized, and controlled in order to achieve acceptable board mount yields. Top Package Figure 1: POP construction cocs4#ier Ared Gc) aliability EndGaer astad liaiXLity Figure 2: schematic of simultaneous reflow Due to the const...

A study was initiated in order to thermally quantify the characteristics of package-on-package (POP), which has been deployed in multiple mobile devices in order to reduce board area and subsequently mobile device size [1,2]. In most POP scenarios (see Figure 1), the memory package is stacked on top of a baseband or application processor and reflowed together. Thermal simulations were conducted for a POP package configuration following the test methods defined in the JEDEC [3] standards and MIL specification [4] for determining junction-to-board ( JB ), and junction-to-case ( JC ) thermal resistances. Enabling a direct correlation with the component-level simulations and experiments, junctionto-board and junction-to-case temperature data were collected for a simulated package on a JEDEC test board. Top and bottom packages for the POP were fabricated using thermal die to enable measurement of junction temperatures. Complementing the baseline simulations and test data, parametric simulation studies were conducted at a component and system level to determine the device and system properties that have the greatest impact on component and system level thermal resistances for POP type devices. The principal purpose of this study was to find a method for estimating die junction temperatures in both the top and bottom packages of a POP configuration assuming the die in both packages dissipate heat. A complex thermal resistance for  JB is proposed to calculate the junction temperatures of memory and base-band integrated circuits (IC) on the phone board from measurable board temperatures under use conditions. Results of the simulation and experimental study will be discussed in the following sections.

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