A study was initiated in order to thermally quantify the characteristics of package-on-package (POP), which has been deployed in multiple mobile devices in order to reduce board area and subsequently mobile device size [1,2]. In most POP scenarios (see Figure 1), the memory package is stacked on top of a baseband or application processor and reflowed together. Thermal simulations were conducted for a POP package configuration following the test methods defined in the JEDEC [3] standards and MIL specification [4] for determining junction-to-board ( JB ), and junction-to-case ( JC ) thermal resistances. Enabling a direct correlation with the component-level simulations and experiments, junctionto-board and junction-to-case temperature data were collected for a simulated package on a JEDEC test board. Top and bottom packages for the POP were fabricated using thermal die to enable measurement of junction temperatures. Complementing the baseline simulations and test data, parametric simulation studies were conducted at a component and system level to determine the device and system properties that have the greatest impact on component and system level thermal resistances for POP type devices. The principal purpose of this study was to find a method for estimating die junction temperatures in both the top and bottom packages of a POP configuration assuming the die in both packages dissipate heat. A complex thermal resistance for  JB is proposed to calculate the junction temperatures of memory and base-band integrated circuits (IC) on the phone board from measurable board temperatures under use conditions. Results of the simulation and experimental study will be discussed in the following sections.

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