Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF

Abstract

This paper proposes a new methodology to accurately predict the impact of inductance on on-chip wire delay using response surface functions (RSF). The proposed methodology consists of two stages which involves first calculating the delay difference between RC and RLC wire models for a set of parameter variations, then building RSFs using electrical parameters such as wire resistance, capacitance, etc. , and physical parameters such as wire width, pitch, etc. as variables. The proposed methodology can help 1) to define design rules for avoiding inductance effects, 2) to point out wires that require RLC delay calculation, and 3) to estimate and correct the delay when using an RC model. An example design rule for limiting self inductance and accurate estimation of the delay difference for a 100 nm technology node is also presented.

On the impact of on-chip inductance on signal nets under the influence of power grid noise

“…Rather, we present the experimental results to show the impact of nonideal power supply conditions on interconnect delays through inductive coupling. The existing studies on interconnect delay with inductive coupling [19]- [21] often assume ideal power supply conditions in nearby power supply grid. With increasing circuit density and increasing switching current, such a treatment may result in inaccurate delays of interconnects.…”

Design and Measurement of an Inductance-Oscillator for Analyzing On-Chip Inductance Impact on Wire Delay

“…Even when the mesh structure is adopted, wire inductance still varies according to the relative position inside the mesh grid spacing. The use of analytical formulae for rapid estimation and evaluation of the inductance [6,7], or quantitative evaluation of the inductance impact using statistical methodology have been proposed [8]. However, unknown factors still exist for modeling inductance, such as the contribution of silicon substrate to the current return path.…”