Achievement of low temperature chip stacking by a wafer-applied underfill material

Abstract

This paper will highlight recent developments of an efficient assembly technology for chip stacking which utilizes a novel wafer applied underfill (WAUF). The a-stage WAUF was spin coated on an 8" wafer with a bump structure of 5 um Cu / 3 um Ni / 5 um Sn2.5Ag Pb-free solder, and then baked at 125ºC for 40 minutes to form a 30 um thick b-stage film. After wafer dicing, four chips with WAUF were assembled via a SÜSS FC-150 bonder on a Si interposer. With the aid of the flux agent in the WAUF, the peak bonding temperature was lowered to 240ºC, which was beneficial for the reduction of residual thermal stress as compared to that imposed by direct bonding at 280ºC. Previous work showed that no delamination of WAUF was found in the chip stacking architecture after the precondition test. In the most recent study, a temperature cycling test (TCT, JESD22-A104-B, Condition B, Soak mode 2) was used to assess the reliability of the 20 um pitch microjoints sealed by the WAUF. After 250 TCT cycles, 87.5% test vehicles failed with a failure mode of the microjoints shown to be interfacial fracture. This was a similar result to the failure mode of microjoints sealed by capillary underfill, though the WAUF failed much earlier.The root-cause of the failure can be attributed to the inferior bonding accuracy, as the majority of the Sn2.5Ag solder alloy at the contact area completely reacted with Ni to form Ni 3 Sn 4 at this stage but did not link up with each other (a proposed failure mechanism will be given in another ITRI's paper). However, the lifespan of the microjoints could be prolonged if the remaining Sn2.5Ag Pb-free solder alloy is sufficient to sustain the bump structure after bonding, even though the WAUF was not post-cured. The authors believe that the newly developed underfill material and the corresponding assembly technology will reveal a proper technique for stacking homogeneous ICs (such as DRAM) efficiently and reliably.

Recent Advances and New Trends in Nanotechnology and 3D Integration for Semiconductor Industry

“…This test vehicle can be degenerated to the case of: (a) wide I/O memory if there is not the memory-chip stacking nor the TSVs in the mechanical/thermal chips and the interposer is either an logic, microprocessor, or SoC; (b) wide I/O DRAM if there are not mechanical and thermal chips and the interposer is a logic chip; and (c) wide I/O interface if there is not the memory-chip stacking and there is not any TSV in the thermal/ mechanical chips. Thus, the core enabling technologies (such as via etching, dielectric, barrier and seed layers deposition, via filling, CMP, thin-wafer handling, electrical and thermal design and test of TSVs, wafer bumping of ultra finepitch lead-free microbumps, fluxless C2W bonding, electronmigration of microbumps, and reliability of microbump assemblies) developed [19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36] with this test vehicle are very useful and can have very broad applications. surrounding Si as shown in Figure 9.…”

A study on the 3DIC interconnection using thermal compression bond with non conductive paste process

“…Scanning Acoustic Microscope (SAM) analysis was carried out to investigate the void formation or non-filled area by TCNCP. Because of the solder melting temperature, the gas of the decomposed NCP may lead to the vigorous void [8,9]. The influence of pre-heat time and stage temperature were examined.…”

Assembly and reliability assessment of 50µm-thick chip stacking by wafer-level underfill film

“…It could remove the oxide layer on solder bump and perform the underfill dispensing in one-step bonding process. Some researchers focus on the materials development such as Nonconductive paste (NCP) [1][2], non-conductive film (NCF) and wafer level underfill (WLUF) [3][4][5][6][7].…”