Achieving side-channel protection with dynamic logic reconfiguration on modern FPGAs

Sasdrich, Pascal; Moradi, Amir; Mischke, Oliver; Güneysu, Tim

doi:10.1109/hst.2015.7140251

Cited by 34 publications

(20 citation statements)

References 2 publications

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“…The side-channel countermeasure using RLUT, shown in [10] is different from the proposed design architecture. The design of [10] implements standard Boolean masking scheme, where each round uses a different mask.…”

Section: Sbox Scrambling For Dpa Resistancementioning

confidence: 95%

“…Nevertheless, LUT based s-box scrambling scheme could be an attractive choice for lightweight cipher due to its less overhead. Additionally, RLUT-based side-channel resistant solutions can be also combined with other side-channel countermeasures as shown in [10].…”

Section: Sbox Scrambling For Dpa Resistancementioning

confidence: 99%

“…The design of [10] implements standard Boolean masking scheme, where each round uses a different mask. Here, we propose a lightweight architecture of SBox scrambling scheme presented in [3].…”

Section: Sbox Scrambling For Dpa Resistancementioning

confidence: 99%

“…To the best of our knowledge, RLUTs have found relevant use in pattern matching and filter applications [9]. Side-channel protection methodology using RLUT is presented in [10] where the authors have combined different side-channel protection strategies with RLUTs and have developed leakageresilient designs. In [11], authors propose a hardware Trojan to leak a secret key of PRESENT [12] cipher.…”

Section: Introductionmentioning

confidence: 99%

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The Conflicted Usage of RLUTs for Security-Critical Applications on FPGA

et al. 2018

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Modern field programmable gate arrays (FPGAs) have evolved significantly in recent years and have found applications in various fields like cryptography, defense, aerospace, and many more. The integration of FPGA with highly efficient modules like DSP and block RAMs has increased the performance of FPGA significantly. This paper addresses the lesser explored feature of modern FPGA called as reconfigurable LUT (RLUT) whose content can be updated internally, even during runtime. We describe the basic functionality of RLUT and discuss its potential applications for security from both destructive and constructive point of view, highlighting the conflicted usage of RLUTs. Several use cases exploiting RLUT feature in security-critical scenarios (physical attacks related in particular) are studied in detail. The paper proposes design of stealthy hardware Trojans having zero payload overhead to highlight destructive applications which can be built using hardware Trojans. On the other hand, this paper also highlights several constructive applications based on RLUT features, starting from lightweight side-channel countermeasures to kill switch to prevent the FPGA hardware from environmental hazards and malicious attack attempts.

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Section: Sbox Scrambling For Dpa Resistancementioning

confidence: 95%

Section: Sbox Scrambling For Dpa Resistancementioning

confidence: 99%

Section: Sbox Scrambling For Dpa Resistancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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The Conflicted Usage of RLUTs for Security-Critical Applications on FPGA

et al. 2018

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“…DLR accomplishes this by selecting among multiple redundant copies of functions programmed into the FPGA fabric, while DPR introduces physical changes to the placement and routing (P&R) structure of the functions by reprogramming the FPGA. Sasdirch et al [15] propose a DLR technique for the PRESENT cipher by combining multiple copies of Xilinx Configurable Lookup Tables (LUTs) to define reconfigurable function tables. In another work [16], the authors propose a masked LUT scheme for implementing block memory content scrambling, which leverages Xilinx SLICE-M LUTs for building randomly permuted (masked) SBOXs.…”

Section: Introductionmentioning

confidence: 99%

Side-Channel Power Resistance for Encryption Algorithms Using Implementation Diversity

et al. 2020

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This paper investigates countermeasures to side-channel attacks. A dynamic partial reconfiguration (DPR) method is proposed for field programmable gate arrays (FPGAs)s to make techniques such as differential power analysis (DPA) and correlation power analysis (CPA) difficult and ineffective. We call the technique side-channel power resistance for encryption algorithms using DPR, or SPREAD. SPREAD is designed to reduce cryptographic key related signal correlations in power supply transients by changing components of the hardware implementation on-the-fly using DPR. Replicated primitives within the advanced encryption standard (AES) algorithm, in particular, the substitution-box (SBOX)s, are synthesized to multiple and distinct gate-level implementations. The different implementations change the delay characteristics of the SBOXs, reducing correlations in the power traces, which, in turn, increases the difficulty of side-channel attacks. The effectiveness of the proposed countermeasures depends greatly on this principle; therefore, the focus of this paper is on the evaluation of implementation diversity techniques.

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