Achieving Zero Switching Loss in Silicon Carbide MOSFET

Li, Xuan; Li, Xu; Liu, Pengkun; Guo, Suxuan; Zhang, Liqi; Huang, Alex Q.; Deng, Xiaochuan; Zhang, Chao

doi:10.1109/tpel.2019.2906352

Cited by 47 publications

(23 citation statements)

References 21 publications

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“…In this section, the proposed concepts are experimentally evaluated on commercial devices, providing further insights on the implications of R s and tan(δ). The loss tangents and the related percentage losses (with respect to an effective stored energy 1 2 C eff oss • V 2 p ) with the excitation frequency (up to 50 MHz) are plotted in Fig. 4(a) for different device structures: Si, SiC, and GaN power devices with similar current ratings on the high-voltage range (500-900 V) are considered.…”

Section: Resultsmentioning

confidence: 99%

“…The product C oss0 • R s0 is a unique feature of a device structure/family that is independent of its current rating. To infer its relation to E diss , R s is considered as a perturbation element, 1 Sizing is also commonly referred to as the scaling-up of a device in deviceengineer terminology. Increasing the device width (e.g.…”

Section: R S and The C Oss Loss Tangentmentioning

confidence: 99%

“…W IDE-Band-Gap (WBG) devices have paved the way to push the boundaries of power conversion in the MHz range, especially for soft-switching and resonant power converters [1]- [3]. One of the major factors that hinders this trend is the non-recoverable power losses associated with device output capacitance, C o (where the corresponding smallsignal quantity is defined as C oss in device data sheets [4]).…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

$C_{\text{oss}}$ Loss Tangent of Field-Effect Transistors: Generalizing High-Frequency Soft-Switching Losses

Perera¹,

Nikoo²,

Jafari³

et al. 2020

IEEE Trans. Power Electron.

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The dissipated energy (E diss) related to the resonant charging/discharging of a transistor output capacitance, becomes a dominant loss factor for power converters operating in the MHz range. A recent work has introduced a small-signal measurement method to quantify E diss with a frequency-dependent small-signal resistance, Rs, and an effective small-signal output capacitance, C eff oss. This work provides further insights on the effect of Rs and Coss upon the device losses in a broader sense. In particular, the Coss loss tangent, tan (δ), is introduced as a normalized E diss to combine the roles of Rs and Coss together with the operating frequency into a single loss parameter. By evaluating commercial device families, it is demonstrated that tan (δ) is constant for a given family, independent of the device on-state resistance, R DS(on). It is shown that a minimum E diss is achieved by having the lowest tan (δ) for a given stored energy (Eoss) in Coss. With accompanying guidelines, this work identifies tan (δ) as a powerful figure of merit to classify field-effect transistors for softswitching applications, regardless of R DS(on) variations in devices within a family. The proposed concept provides a comprehensive method to characterize and benchmark power transistors for high-frequency applications.

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Section: Resultsmentioning

confidence: 99%

Section: R S and The C Oss Loss Tangentmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

$C_{\text{oss}}$ Loss Tangent of Field-Effect Transistors: Generalizing High-Frequency Soft-Switching Losses

Perera¹,

Nikoo²,

Jafari³

et al. 2020

IEEE Trans. Power Electron.

View full text Add to dashboard Cite

show abstract

“…At t = t2, the FET is turned OFF. The resonance between L and COSS provides a zero turn-OFF loss (ZTL) [9]: because the switching time (∆tSW) is much faster than √ OSS time constant, the cross product of the channel current (ich) and drain-source voltage (vDS) is completely negligible. The resonance between L and COSS results in the formation of an impulse waveform over drain-source terminals of the FET, as…”

Section: Introductionmentioning

confidence: 99%

Efficient High Step-Up Operation in Boost Converters Based on Impulse Rectification

Nikoo

Jafari

Perera

et al. 2020

IEEE Trans. Power Electron.

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Conventional boost converters, while having a high level of simplicity and robustness, are known to have a poor efficiency at high step-up regime. More complicated topologies have been extensively explored to increase the step-up ratio while keeping a high-efficiency, however, an efficient regulated dc-dc power conversion at high step-up regime still remains a challenge. In this work we demonstrate fully soft-switched operation of boost converters based on impulse rectification, which results in an efficient power conversion at very high step-up regime. Contrary to the conventional analysis of boost converters which seeks to minimize conduction and switching losses, our approach considers reactive power as the key parameter limiting efficiency. A theoretical basis for this operation mode enabled an appropriate design resulting in power conversion efficiencies above 90% for voltage gain values of 5, 10, 25, and 50, with a peak efficiency of 97%. The guidelines to design boost converters based on the proposed approach are discussed. The simplicity and high performance of this approach opens new avenues in designing regulated dc-dc converters with a high step-up.

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“…OMPARED with silicon power devices, silicon carbide (SiC) power devices possess lower power loss, higher operation temperature, higher switching frequency, and better heat dissipation owing to its superior material properties, such as wider bandgap, higher critical electric field strength, and higher thermal conductivity [1]- [3]. Hereby SiC power devices are expected to be next-generation alternatives to silicon power devices in power conversion systems.…”

Section: Introductionmentioning

confidence: 99%

Different JFET Designs on Conduction and Short-Circuit Capability for 3.3 kV Planar-Gate Silicon Carbide MOSFETs

Chen

et al. 2020

IEEE J. Electron Devices Soc.

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Both large current capability and strong short-circuit (SC) ruggedness are necessary for 3.3 kV SiC MOSFETs to improve system efficiency and reduce costs in industrial and traction applications. In this paper, the effects of Junction Field Effect Transistor (JFET) region width and JFET doping (JD) on conduction and SC capability of the 3.3 kV planar-gate SiC MOSFETs are systematically investigated by experiments and simulations. When the JFET width (WJFET) of device without JD is smaller, the positive temperature coefficient of the special on-resistance (Ron,SP) is larger. The JD is effective to improve the Ron,SP, but excessive electric field in gate oxide induced by JD should be paid more attention. The optimization of WJFET can be used to improve both Ron,SP and short circuit withstanding time (SCWT) at the same time. The drain-source current (Ids) and SCWT of the optimized devices are 50 A and more than 20 μs, respectively, which is state-of-the-art for 3.3 kV SiC MOSFETs.

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Achieving Zero Switching Loss in Silicon Carbide MOSFET

Cited by 47 publications

References 21 publications

$C_{\text{oss}}$ Loss Tangent of Field-Effect Transistors: Generalizing High-Frequency Soft-Switching Losses

$C_{\text{oss}}$ Loss Tangent of Field-Effect Transistors: Generalizing High-Frequency Soft-Switching Losses

Efficient High Step-Up Operation in Boost Converters Based on Impulse Rectification

Different JFET Designs on Conduction and Short-Circuit Capability for 3.3 kV Planar-Gate Silicon Carbide MOSFETs

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