Nanometer-scale transistors based on III-V compound semiconductors, such as GaAs, InAs, and InP, are at the heart of many high-speed and high-frequency electronic systems 10. Due to their high electron mobilities, these devices exhibit very high small-signal cutoff frequencies, in the terahertz range 11. However, the high-frequency large-signal performance of transistors is still a challenge, since it is severely limited by the output capacitance Cout, electron saturation velocity and critical electric field 12. The maximum switching speed of a transistor (Fig. 1a) with saturation current Imax is limited to performance semiconductor materials. GaAs and InP are limited to the JFOM, while Cout-limited rise-rate of 1 V/ps restricts the performance of SiC, GaN, and Diamond.

Soft-switching power converters based on wideband-gap (WBG) transistors offer superior efficiency and power density advantages. However, at high frequencies, loss behavior varies significantly between different WBG technologies. This includes losses related to conduction and dynamic ON-resistance (RDS(ON)) degradation, also charging/discharging of input capacitance (CISS) and output capacitance (COSS). As datasheets lack such important information, we present measurement techniques and evaluation methods for soft-switching losses in WBG transistors which enable a detailed loss-breakdown analysis. We estimate the gate loss under soft-switching conditions using a simple small-signal measurement. Next, we use Sawyer-Tower (ST) and Nonlinear Resonance (NR) methods to measure largesignal COSS energy losses up to 40 MHz. Finally, we investigate the dependence of dynamic RDS(ON) degradation on OFF-state voltage using pulsed-IV measurements. We demonstrate an insightful comparison of soft-switching losses for various normally-OFF Gallium-Nitride (GaN) and Silicon-Carbide (SiC) devices. A p-GaN-gated device exhibits the most severe RDS(ON) degradation and the lowest gate loss. Cascode arrangement increases threshold voltage for GaN devices and reduces gate losses in SiC transistors; however, it leads to higher COSS losses. The study facilitates the evaluation of system losses and selection of efficient WBG devices based on the trade-offs between various sources of losses at high frequencies.

Gallium nitride (GaN) power devices are employed in an increasing number of applications thanks to their excellent performance. Nevertheless, their potential for cryogenic applications, such as space, aviation, and superconducting systems, has not yet been fully explored. In particular, little is known on the device performance below liquid nitrogen temperature (77 K) and the behavior of popular GaN architectures such as Gate Injection Transistor (GIT) and Cascode below room temperature has not yet been reported. Most importantly, it is still unclear how the different device loss contributions, i.e. conduction, soft-and hard-switching losses, change at cryogenic temperatures. In this work, we investigate and compare the performance of four GaN commercial power devices in a wide temperature range between 400 K and 4.2 K. All of the tested devices can successfully operate at cryogenic temperature with an overall performance improvement. However, different GaN HEMT technologies lead to significant variations in device gate control and loss mechanisms, which are discussed based on the device structure. The presented results prove the promising potential of the GaN technology for lowtemperature applications and provide precious insights to properly design power systems operating under cryogenic temperatures and maximize their efficiency.

In this letter, we present a new measurement technique to evaluate the large-signal output capacitance (COSS) of transistors as well as the COSS energy dissipation (EDISS), based on the nonlinear resonance between a known inductor and the output capacitance of the device under test. The method is simple and robust, and only requires a single voltage measurement to extract the large-signal COSS both in charging and discharging transients. By changing the circuit parameters, it is possible to tune the resonance frequency (even above 40 MHz) and the voltage swing (even above 1 kV) with dv/dt exceeding 100 V/ns, even though the method relies only on a low-voltage DC source, without the need for high-voltage RF amplifiers. The single-pulse operation of the method enables measuring COSS and EDISS at very high frequency and dv/dt values without any thermal runaway. Using the proposed method, we extracted large-signal COSS and EDISS of power transistors based on different semiconductor technologies. The obtained results were verified by Sawyer-Tower method and data reported in the literature. The precise characterization of large-signal COSS of transistors presented in this letter is essential for the design of power converters, especially those operating at high switching frequencies.

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