Active inductor for power-supply decoupling in mixed signal systems

Taparia, A.; Viswanathan, T.R.; Banerjee, Bhaskar

doi:10.1109/dcas.2008.4695916

Cited by 3 publications

(3 citation statements)

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“…The Q of the active inductor can be written as follows (when seen as a parallel R-L-C) neglecting the output conductance of M1 [7]:…”

Section: Proposed Active Inductormentioning

confidence: 99%

“…In this paper, an attempt to manage the switching transients generated by digital CMOS gates by localizing them in the same region of their origin [9], thus preventing them from coupling to other analog systems on the same substrate. Fig.1.…”

Section: Introductionmentioning

confidence: 99%

“…4(a)-(c)] have low input impedance owing to the transistor M1 operated in the common-gate con-figuration. All of them provide inductive behavior as each of the circuits act as a gyrator [7]. The voltage at node X ( Fig.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Power Supply Noise Rejection Circuit using Active Inductor and Active Capacitor in Mixed Signal Systems

Elanagai¹,

Manikannan²,

Nivetha³

et al. 2015

IJERT

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System integrity is emerging as an important issue as very large scale integration (VLSI) technology advances to nanoscale regime. This rise to system-on-chip (SoC) concept, due to this several systems is included such as rf, optical, etc. In mixed-signal system, both analog and digital circuits are being integrated in to a same chip. In this case power-supply noise is a significant problem in mixed-signal systems on a chip. This is due to the impulse like currents drawn by the CMOS gates during transitions cause noise in the sensitive analog circuits via power supply/ground (PG) and substrate. These unwanted variations in PG network is found to be most dominant source of substrate noise currents injected into the substrate. The switching noise generated by the CMOS gates also couple into sensitive analog blocks via the bonding wires and the shared PG buses. A noise-localization technique using on-chip active inductors along with an active decoupling capacitance using nmos is proposed. This would make the noise current generated by the digital gates to remain local in the region of the digital gates as well as reduction in the area of the circuit. This active inductor and active capacitor is designed using GDPK 90nm and 45nm CMOS technology.

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“…The Q of the active inductor can be written as follows (when seen as a parallel R-L-C) neglecting the output conductance of M1 [7]:…”

Section: Proposed Active Inductormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%