Adapting the RACER Architecture to Integrate Improved In-ReRAM Logic Primitives

Abstract

Modern computing applications based upon machine learning can incur significant data movement overheads in state-of-the-art computers. Resistive-memory-based processing-using-memory (PUM) can mitigate this data movement by instead performing computation in situ (i.e., directly within memory cells), but device-level limitations restrict the practicality and/or performance of many PUM architecture proposals. The RACER architecture overcomes these limitations, by proposing efficient peripheral circuitry and the concept of bit-pipelining to enable high-performance, high-efficiency computation using small memory tiles. In this work, we extend RACER to adapt easily to different PUM logic families, by (1) modifying the device access circuitry to support a wide range of logic families, (2) evaluating three logic families proposed by prior work, and (3) proposing and evaluating a new logic family called OSCAR that significantly relaxes the switching voltage constraints required to perform logic with resistive memory devices. We show that the modified RACER architecture, using the OSCAR logic family, can enable practical PUM on real ReRAM devices while improving performance and energy savings by 30% and 37%, respectively, over the original RACER work.

Accelerating Neural Network Inference with Processing-in-DRAM: From the Edge to the Cloud

“…One such approach is processing-in-memory (PIM) [74][75][76][77][78][79][80][81][82][83][84][85], where computation is (1) placed near 2D [69, or 3D [45,63,64,67, memory arrays (processing-nearmemory, PNM) or (2) performed using the memory arrays themselves (processingusing-memory, PUM) [65, 70-72, 135, 167-203]. 1 PNM and PUM can be implemented using different memory technologies [75], including SRAM [71,99,107,110,177,178], DRAM [45, 64, 87, 100, 111, 123, 125, 128, 131-135, 142, 143, 146, 152, 157, 193, 195, 196], and resistive RAM (ReRAM) [65,70,121,174,175,183,188,189,199,200,202]. Independent of the memory technology, PIM allows NNs to enjoy higher memory bandwidth, shorter memory access latency, and lower energy per bit [75].…”