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Physical changes occurring in TiN/TaO2.0±0.2/TiN resistive random-access memory devices after prolonged cycling have been analyzed by two scanning transmission electron microscopy modalities: high angle annular dark field and x-ray energy dispersive spectroscopy. In just formed devices, filaments had a shape of a 10 nm diameter Ta-enriched column with the O-rich gap next to electrodes, which was positively biased during electroformation. Devices that failed by stuck-in-high resistance state mode exhibited Ta depletion and oxygen interdiffusion at interfaces with both electrodes akin to effects observed in complementary switching devices. Initially narrow Ta-rich filaments broadened into ∼50 nm diameter columns showing speckled contrast due to phase separation. In devices that failed by stuck-in-low resistance state mode, we have observed a strong Ta-enriched sub-filament bridging the gap. The amount of oxygen in the TiN anode in the vicinity of the filament has not changed significantly between as-formed and failed devices, thus indicating that oxygen is not lost during switching. All devices at the end of endurance exhibited interdiffusion of O into TiN and Ti and N into TaOx.

Modern computing applications based upon machine learning can incur significant data movement overheads in state-of-the-art computers. Resistive-memory-based processing-using-memory (PUM) can mitigate this data movement by instead performing computation in situ (i.e., directly within memory cells), but device-level limitations restrict the practicality and/or performance of many PUM architecture proposals. The RACER architecture overcomes these limitations, by proposing efficient peripheral circuitry and the concept of bit-pipelining to enable high-performance, high-efficiency computation using small memory tiles. In this work, we extend RACER to adapt easily to different PUM logic families, by (1) modifying the device access circuitry to support a wide range of logic families, (2) evaluating three logic families proposed by prior work, and (3) proposing and evaluating a new logic family called OSCAR that significantly relaxes the switching voltage constraints required to perform logic with resistive memory devices. We show that the modified RACER architecture, using the OSCAR logic family, can enable practical PUM on real ReRAM devices while improving performance and energy savings by 30% and 37%, respectively, over the original RACER work.

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