RACER: Bit-Pipelined Processing Using Resistive Memory

Truong, Minh S. Q.; Chen, Eric; Su, Deanyone; Shen, Liting; Glass, Alexander; Carley, L.R.; Bain, James A.; Ghose, Saugata

doi:10.1145/3466752.3480071

Cited by 25 publications

(21 citation statements)

References 57 publications

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“…Hence, other technologies will have similar query execution behavior as PIMDB. [81] also supports direct inter-crossbar communication in addition to bulk-bitwise PIM. This communication enables aggregation without the host, potentially increasing performance further at additional hardware and control costs.…”

Section: Related Workmentioning

confidence: 56%

“…PIM architectures occasionally need inter-crossbar data movements. These data movements can be accomplished indirectly via simple, yet slower, CPU load/store instructions or using faster, but more complex, direct inter-crossbar communication [37,78,81]. Direct inter-crossbar communication can be added to PIMDB at the cost of added hardware and complexity.…”

Section: Column Indexmentioning

confidence: 99%

“…For the filteronly queries, however, only the filter operation is measured (including reading the results), as the rest of the query execution does not involve the PIM modules or their database copy and is considered out-of-scope for this work. Our evaluation does not compare PIMDB to other bulk-bitwise PIM technologies and architectures [25,31,38,49,69,77,81] as we are interested in evaluating bulk-bitwise PIM, not comparing the various technologies. We further discuss this issue in Section VII.…”

Section: A Query Execution Timementioning

confidence: 99%

“…Several bulk-bitwise PIM technologies and architectures were previously proposed [25,31,49,69,77,81]. These works showed how to perform the bulk-bitwise PIM operations, but did not delve into full system performance.…”

Section: Related Workmentioning

confidence: 99%

“…Previous works focused on certain aspects of bulk-bitwise PIM. These aspects include exploration of technology [5,25,49,69,81], programming language abstraction [31,89], memory interface [77], logic design and abstraction [6,30,51], and combining it with other PIM technologies [37,38]. A full-system perspective of bulk-bitwise PIM is, however, still missing.…”

Section: Introductionmentioning

confidence: 99%

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PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics

Perach¹,

Ronen²,

Kimelfeld³

et al. 2022

Preprint

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Bulk-bitwise processing-in-memory (PIM), where large bitwise operations are performed in parallel by the memory array itself, is an emerging form of computation with the potential to mitigate the memory wall problem. This paper examines the capabilities of bulk-bitwise PIM by constructing PIMDB, a fully-digital system based on memristive stateful logic, utilizing and focusing on in-memory bulk-bitwise operations, designed to accelerate a real-life workload: analytical processing of relational databases. We introduce a host processor programming model to support bulk-bitwise PIM in virtual memory, develop techniques to efficiently perform in-memory filtering and aggregation operations, and present the mapping of the application into the memory. When tested against an equivalent in-memory database on the same host system, our approach substantially lowers the number of required memory read operations, thus accelerating TPC-H filter operations by 1.6×-18× and full queries by 56×-608×, while reducing the energy consumption by 1.7×-18.6× and 0.81×-12× for these benchmarks, respectively. Our extensive evaluation uses the gem5 full-system simulation environment.

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Section: Related Workmentioning

confidence: 56%

Section: Column Indexmentioning

confidence: 99%

Section: A Query Execution Timementioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics

Perach¹,

Ronen²,

Kimelfeld³

et al. 2022

Preprint

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Prototyping Reconfigurable RRAM-Based AI Accelerators Using the RISC-V Ecosystem and Digital Twins

Fritscher,

Veronesi,

Baroni

et al. 2023

Lecture Notes in Computer Science

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Experimental demonstration of magnetic tunnel junction-based computational random-access memory

Lv,

Zink,

Bloom

et al. 2024

npj Unconv. Comput.

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The conventional computing paradigm struggles to fulfill the rapidly growing demands from emerging applications, especially those for machine intelligence because much of the power and energy is consumed by constant data transfers between logic and memory modules. A new paradigm, called “computational random-access memory (CRAM),” has emerged to address this fundamental limitation. CRAM performs logic operations directly using the memory cells themselves, without having the data ever leave the memory. The energy and performance benefits of CRAM for both conventional and emerging applications have been well established by prior numerical studies. However, there is a lack of experimental demonstration and study of CRAM to evaluate its computational accuracy, which is a realistic and application-critical metric for its technological feasibility and competitiveness. In this work, a CRAM array based on magnetic tunnel junctions (MTJs) is experimentally demonstrated. First, basic memory operations, as well as 2-, 3-, and 5-input logic operations, are studied. Then, a 1-bit full adder with two different designs is demonstrated. Based on the experimental results, a suite of models has been developed to characterize the accuracy of CRAM computation. Scalar addition, multiplication, and matrix multiplication, which are essential building blocks for many conventional and machine intelligence applications, are evaluated and show promising accuracy performance. With the confirmation of MTJ-based CRAM’s accuracy, there is a strong case that this technology will have a significant impact on power- and energy-demanding applications of machine intelligence.

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RACER: Bit-Pipelined Processing Using Resistive Memory

Cited by 25 publications

References 57 publications

PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics

PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics

Prototyping Reconfigurable RRAM-Based AI Accelerators Using the RISC-V Ecosystem and Digital Twins

Experimental demonstration of magnetic tunnel junction-based computational random-access memory

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