Adaptive Algorithm and Tool Flow for Accelerating SystemC on Many-Core Architectures

Roth, Christoph; Reder, Simon; Bucher, Harald; Sander, Oliver; Becker, J.

doi:10.1109/dsd.2014.62

Cited by 8 publications

(3 citation statements)

References 18 publications

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“…This article is based on the conference paper [27]. Major parts of the described work are also presented in the PhD thesis of Christoph Roth [28].…”

Section: Acknowledgementsmentioning

confidence: 99%

Adaptive algorithm and tool flow for accelerating SystemC on many-core architectures

Reder

Roth

Bucher

et al. 2015

Microprocessors and Microsystems

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“…This article is based on the conference paper [27]. Major parts of the described work are also presented in the PhD thesis of Christoph Roth [28].…”

Section: Acknowledgementsmentioning

confidence: 99%

Adaptive algorithm and tool flow for accelerating SystemC on many-core architectures

Reder

Roth

Bucher

et al. 2015

Microprocessors and Microsystems

Self Cite

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“…In [21], authors studied parallel simulation of SystemC using Intel Single-chip Cloud Computer (SCC) [22] which has 48 cores connected by a 2D mesh network. The simulation algorithm is also based on CMB.…”

Section: Vcsmentioning

confidence: 99%

ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment

Sato

Kobayashi

Kise

2018

IEICE Trans. Inf. & Syst.

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LSIs are generally designed through four stages including architectural design, logic design, circuit design, and physical design. In architectural design and logic design, designers describe their target hardware in RTL. However, they generally use different languages for each phase. Typically a general purpose programming language such as C or C++ and a hardware description language such as Verilog HDL or VHDL are used for architectural design and logic design, respectively. That is time-consuming way for designing a hardware and more efficient design environment is required. In this paper, we propose a new hardware modeling and high-speed simulation environment for architectural design and logic design. Our environment realizes writing and verifying hardware by one language. The environment consists of (1) a new hardware description language called ArchHDL, which enables to simulate hardware faster than Verilog HDL simulation, and (2) a source code translation tool from ArchHDL code to Verilog HDL code. ArchHDL is a new language for hardware RTL modeling based on C++. The key features of this language are that (1) designers describe a combinational circuit as a function and (2) the ArchHDL library realizes non-blocking assignment in C++. Using these features, designers are able to write a hardware transparently from abstracted level description to RTL description in Verilog HDL-like style. Source codes in ArchHDL is converted to Verilog HDL codes by the translation tool and they are used to synthesize for FPGAs or ASICs. As the evaluation of our environment, we implemented a practical many-core processor in ArchHDL and measured the simulation speed on an Intel CPU and an Intel Xeon Phi processor. The simulation speed for the Intel CPU by ArchHDL achieves about 4.5 times faster than the simulation speed by Synopsys VCS. We also confirmed that the RTL simulation by ArchHDL is efficiently parallelized on the Intel Xeon Phi processor. We convert the ArchHDL code to a Verilog HDL code and estimated the hardware utilization on an FPGA. To implement a 48-node many-core processor, 71% of entire resources of a Virtex-7 FPGA are consumed.

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“…This severely limits the execution speed of SystemC simulation.In order to provide faster execution, parallel discrete event simulation (PDES) [8,12] techniques can be applied. While significant obstacles exist specifically for the SystemC language [7], many parallel simulation approaches have been proposed [5,11,19,[21][22][23][24]. Beyond these synchronous PDES techniques, out-of-order PDES [6] is even more aggressive.…”

mentioning

confidence: 99%

Pushing the Limits of Parallel Discrete Event Simulation for SystemC

Dömer

Cheng

Mendoza

et al. 2020

A Journey of Embedded and Cyber-Physical Systems

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The IEEE standard SystemC language [13] is widely used for the specification, modeling, validation, and evaluation of electronic system level (ESL) models. The Accellera Systems Initiative maintains not only the official SystemC language definition, but also provides an open source proof-of-concept library that can be used to simulate SystemC design models [1]. However, implementing the classic scheme of discrete event simulation (DES), this reference simulator runs sequentially and cannot utilize the parallel computing resources available on multi-and many-core processor hosts. This severely limits the execution speed of SystemC simulation.In order to provide faster execution, parallel discrete event simulation (PDES) [8,12] techniques can be applied. While significant obstacles exist specifically for the SystemC language [7], many parallel simulation approaches have been proposed [5,11,19,[21][22][23][24]. Beyond these synchronous PDES techniques, out-of-order PDES [6] is even more aggressive. By localizing the simulation time to individual threads and carefully handling events at different times, the simulator engine can issue threads in parallel and ahead of time, following a partial ordering without loss of accuracy. This results in better exploitation of the available parallelism and thus maximum simulation speed.The Recoding Infrastructure for SystemC (RISC) project described in this paper implements out-of-order PDES for the IEEE SystemC language as open source. Specifically, RISC provides a dedicated SystemC compiler and corresponding outof-order parallel simulator [2,8,16]. Compared to the other approaches, RISC automatically analyzes the SystemC source code, identifies all potential race condi-R. Dömer ( ) • Z.

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Adaptive Algorithm and Tool Flow for Accelerating SystemC on Many-Core Architectures

Cited by 8 publications

References 18 publications

Adaptive algorithm and tool flow for accelerating SystemC on many-core architectures

Adaptive algorithm and tool flow for accelerating SystemC on many-core architectures

ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment

Pushing the Limits of Parallel Discrete Event Simulation for SystemC

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