No abstract

Abstract-Embedded software is playing an increasing role in todays SoC designs. It allows a flexible adaptation to evolving standards and to customer specific demands. As software emerges more and more as a design bottleneck, early, fast, and accurate simulation of software becomes crucial. Therefore, an efficient modeling of programmable processors at high levels of abstraction is required.In this article, we focus on abstraction of computation and describe our abstract modeling of embedded processors. We combine the computation modeling with task scheduling support and accurate interrupt handling into a versatile, multi-faceted processor model with varying levels of features.Incorporating the abstract processor model into a communication model, we achieve fast co-simulation of a complete custom target architecture for a system level design exploration. We demonstrate the effectiveness of our approach using an industrial strength telecommunication example executing on a Motorola DSP architecture. Our results indicate the tremendous value of abstract processor modeling. Different feature levels achieve a simulation speedup of up to 6600 times with an error of less than 8% over a ISS based simulation. On the other hand, our full featured model exhibits a 3% error in simulated timing with a 1800 times speedup.

In this paper, we extend the set of library components which are usually considered in architectural synthesis by components with built-in chaining. For such components, the result of some internally computed arithmetic function is made available as an argument to some other function through a local connection. These components can be used to implement chaining i n a data-path in a single component. Components with built-in chaining are combinatorial circuits.They correspond to "complex gates" in logic synthesis. If compared to implementations with several components, components with builtin chaining usually provide a denser layout, reduced power consumption, and a shorter delay time. Multiplier/accumulators are the most prominent example of such components. Such components require new approaches for library mapping in architectural synthesis. In this paper, we describe an IP-based approach taken in our OSCAR synthesis system. I. MOTIVATIONArchitectural synthesis (also known as hzgh-level syntheszs (HLS)) can be defined as the task of implementing a given behavioural specification by means of an appropriate register-t ransfer (RT-) level architecture. Architectural synthesis is considered to provide the next productivity boost for designers of information-processing devices.RT-level components, which have been considered so far, include registers, register-files, busses, multiplexers and multi-functional units (ALUs). All functional units were considered to compute essentially a single (possibly control-selectable) standard function] such as addition, subtraction] or multiplication. On the other hand, current component libraries contain a growing number of components with buzlt-zn chaznzng (BIG') or znternal chaznzng. With built-in chaining] the result of some computed *standard function is made available as an argument to another function. For example, multzplzer/adders multiply two numbers and add the result to a third one (see fig. 1). With BIC components, chaining in HLS can be implemented by a single component. In contrast] standard chaining requires external wiring be tween two or more components (therefore, we call it exterrial chaznzng). Figure 1: Multiplier/adderIn addition to multiplierladders, multiplier/adder/accumulators (MACS), ALUs followed by (internal) shifters, and adders followed by (internal) comparators are componeiits with internal chaining.The main advantages of such components include:The ability to generate eficzent layout. The layout of BIG components is usually more efficient than the combined layout of several independently designed functional units. For example, abutment of corresponding lines may be possible.Delay and power consumption m a y be smaller than for separate components. The delay of BIC components may be small due to a) the more compact layout, b) exploitation of context-dependent information during logic synthesis] and c) adjustment of the strength of drivers. Design-reuse of complex components as facilitated.Exploiting the presence of BIC components is important for re-...

Abstract-To meet the challenge of increasing design complexity, designers are turning to system level design languages (SLDLs) to model systems at a higher level of abstraction. This paper presents a method of automatically generating embedded software from system specification written in SLDL. Several refinement steps and intermediate models are introduced in our software generation flow. We demonstrate the effectiveness of the proposed method by a tool which can generate efficient ANSI C code from system models written in SLDL.

Abstract-With growing market pressures and rising system complexities, automated system-level communication design with efficient design space exploration capabilities is becoming increasingly important. At the same time, customized network-oriented communication architectures become necessary in enabling a high-performance communication among the system components. To this end, corresponding communication design flows that are supported by efficient design automation techniques need to be developed. In this paper, we present a system-level design environment for the generation of bus-based system-on-chip architectures. Our approach supports a two-stage design flow using automated model refinement toward custom heterogeneous communication networks. Starting from an abstract specification of the desired communication channels, our environment automatically generates tailored network models at various levels of abstraction. At its core, an automatic layer-based refinement approach is utilized. We have applied our approach to a set of industrial-strength examples with a wide range of target architectures. Our experimental results show significant productivity gains over a traditional communication design, allowing early and rapid design space exploration.Index Terms-Communication synthesis, embedded systems, heterogeneous multiprocessor system-on-chip (MPSoC), systemlevel design, transaction-level modeling (TLM).