System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design

Dömer, Rainer; Gerstlauer, Andreas; Peng, Junyu; Shin, Dongwan; Cai, Lukai; Yu, Haobo; Abdi, Samar; Gajski, Daniel D.

doi:10.1155/2008/647953

Cited by 90 publications

(46 citation statements)

References 6 publications

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“…The system-on-chip environment (SCE) [3] is based on the influential SpecC language and methodology. SCE implements a top-down system design flow based on a specify-explore-refine paradigm with support for heterogeneous target platforms consisting of custom hardware components, embedded software processors, dedicated IP blocks, and complex communication bus architectures.…”

Section: Related Workmentioning

confidence: 99%

“…This framework aims at enabling even software developers to easily design complicated systems such as multimedia applications which are rich in data parallelism. For this, we integrate a component technology for embedded software, TECS (TOPPERS Embedded Component System [2]), and the systemon-a-chip environment SCE [3], which is based on SpecC language. Since TECS is based on conventional C language, it allows the developers to start the design process easily and fast.…”

Section: Introductionmentioning

confidence: 99%

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TECSCE: HW/SW Codesign Framework for Data Parallelism Based on Software Component

Azumi

Syahkal

Hara-Azumi

et al. 2013

IFIP Advances in Information and Communication Technology

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Abstract. This paper presents a hardware/software (HW/SW) codesign framework (TECSCE) which enables software developers to easily design complex embedded systems such as massive data-parallel systems. TECSCE is implemented by integrating TECS and SCE: TECS is a component technology for embedded software, and SCE provides an environment for system-on-a-chip designs. Since TECS is based on standard C language, it allows the developers to start the design process easily and fast. SCE is a rapid design exploration tool capable of efficient MPSoC implementation. TECSCE utilizes all these advantages since it supports transformation from component descriptions and component sources to SpecC specification, and lets the developers decide data partitioning and parallelization at a software component level. Moreover, TECSCE effectively duplicates software components, depending on their degree of data parallelizing, to generate multiple SpecC specification models. An application for creating a panoramic image removing objects, such as people, is illustrated as a case study. The evaluation of the case study demonstrates the effectiveness of the proposed framework.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

TECSCE: HW/SW Codesign Framework for Data Parallelism Based on Software Component

Azumi

Syahkal

Hara-Azumi

et al. 2013

IFIP Advances in Information and Communication Technology

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“…For this purpose, we introduce well defined intermediate transaction level models as the canonical interface between various formal models and generic implementations. As a proof of concept, we couple representatives from both classes, namely the SystemCoDesigner [7] and the System-On-Chip Environment (SCE) [8] solutions. We concentrate on bus-based MPSoCs, as these architectures are most common, and memory-mapped bus modeling is the focus of the TLM 2.0 standard [9].…”

Section: Constraintsmentioning

confidence: 99%

“…Automatic refinement for both computation and communication is implemented in the System-On-Chip Environment (SCE) [8]. There, however, no support for automatic decision making is integrated and the refinement process starts from a generic, relatively low-level C-based system model.…”

Section: Related Workmentioning

confidence: 99%

A system-level synthesis approach from formal application models to generic bus-based MPSoCs

Gladigau

Gerstlauer

Haubelt

et al. 2010

2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

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Abstract-System-level synthesis is the task of automatically implementing application models as hardware/software systems. It encompasses four basic sub tasks, namely decision making and refinement for both computation and communication. In the past, several system-level synthesis approaches have been proposed. However, it was shown that each of these approaches has drawbacks in at least one of the four sub tasks. In this paper, we present our efforts towards a comprehensive system-level synthesis by combining two academic system-level solutions into a seamless approach that automatically generates pin-accurate implementation-level models starting from a formal application model and generic MPSoC architecture templates. We analyze the system-level synthesis flow and define intermediate representations in terms of transaction level models that serve as link between existing tools. Furthermore, we present the automated transformation between models for combining two design flows. We demonstrate the combined flow on an industrial-strength example and show the benefits of fully automatic exploration and synthesis for rapid and early system-level design.

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“…In the current system-level design methodologies [6,7], they provide the tools which interactively support the transformations and refinement of a design. In these methodologies, a design is locally and incrementally refined by transforming the design manually.…”

Section: Introductionmentioning

confidence: 99%

Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences

Yoshida

Fujita

2009

2009 10th International Symposium on Quality of Electronic Design

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System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design

Cited by 90 publications

References 6 publications

TECSCE: HW/SW Codesign Framework for Data Parallelism Based on Software Component

TECSCE: HW/SW Codesign Framework for Data Parallelism Based on Software Component

A system-level synthesis approach from formal application models to generic bus-based MPSoCs

Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences

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