Adaptive Boolean Logic Using Ferroelectrics Capacitors as Basic Units of Artificial Neurons and Its Implementation in FPGA

Silva, Alan P. O. da; Leite, Cicília Raquel Maia; McMillan, L. D.; Araújo, Carlos A. Paz de; Fernandes, Marcelo A. C.; Guerreiro, Ana M. G.

doi:10.1080/10584587.2015.1029408

Cited by 2 publications

(2 citation statements)

References 12 publications

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“…The first simulating model to the work of a biological neuron presented by the scientist McCulloch and Pitts in 1943, as computational model for a binary-threshold unit represents an artificial nerve cell operating in separate time by integrating mathematical logic and neurophysiology [29]. The output of the neuron is equals one when the input of the activation function is more than or equivalent to threshold term otherwise the output is equal to -1.…”

Section: Background 21 Artificial Neural Network Principlementioning

confidence: 99%

Implementation three-step algorithm based on signed digit number system by using neural network

Thabit¹,

Dawood²,

Issa³

2021

IJEECS

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The need for a simple and effective system that works with high efficiency features such as high processing speed, the ability to solve problems by learning method and accomplish the largest amount of data processing accurately and in little time produces that system, which attracted the efforts of the researcher to employ neural networks in computing away from the complexities that burden traditional computers. We presented a model for the design of the arithmetic circuit for the process of addition the sign digit numbers in a new way to deal with the arithmetic operations, which employment of the use of neural networks, this model includes a theoretical and practical simulation of them. The model relied on the implementation of the addition process based on a three-step algorithm adopted by the signed systems. Which is characterized by the possibility of execution in a parallel way, and therefore it provides the advantage of completion of arithmetic operation regardless of the length of their operands, or in other words, whatever the number of bits in the operands. The simulation of the model is done by entering operands for 6 addition operations (each one has operands are 15-bit length) to be executed simultaneously.

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Section: Background 21 Artificial Neural Network Principlementioning

confidence: 99%

Implementation three-step algorithm based on signed digit number system by using neural network

Thabit¹,

Dawood²,

Issa³

2021

IJEECS

View full text Add to dashboard Cite

show abstract

“…O uso de soluções em hardware tem se mostrado muito eficiente para auxiliar na execução desses métodos. Implementações realizadas em Field Programmable Gate Array (FPGA) conseguem a obtenção de ótimo desempenho com baixo consumo de energia, devido a paralelização e otimização dos algoritmos a nível de portas lógicas, sendo possível acelerar em até mil vezes o processamento das técnicas comparado às implementações convencionais em software (Silva et al, 2015;Holanda e Fernandes, 2016;Silva et al, 2016;Souza e Fernandes, 2014) O Naive Bayes (NB) é uma técnica de ML bastante utilizada para a resolução de problemas de classificação. Na literatura há alguns trabalhos que implementam o NB em hardware, buscando obter processamento em tempo real para as mais diversas aplicações, como reconhecimento facial e classificação de pacotes de redes (Chou e Chen, 2020;França et al, 2015).…”

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Proposta de Implementação Paralela do Método Naive Bayes em FPGA

Barros

Fernandes

2021

Procedings Do XV Simpósio Brasileiro De Automação Inteligente

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This work proposes a hardware implementation of the Naive Bayes classifier, aiming to develop a fully parallel architecture that aims to obtain high performance in processing speed and energy consumption. The proposed hardware was developed in a Field Programmable Gate Array (FPGA) using a fixed point. All details of the developed architecture are presented, including information regarding the occupation rate of hardware resources, processing time, and energy consumption for an FPGA Stratix V 5SGXMBBR3H43C3. A comparative analysis of the model was carried out with other works of state of the art through the results obtained. It was possible to conclude that the implementation obtained a performance similar or superior to other works in the literature. Resumo: Este trabalho propõe uma implementação em hardware do classificador Naive Bayes, tendo como objetivo o desenvolvimento de uma arquitetura totalmente paralela, que visa obter alta performance em termos de velocidade de processamento e consumo energético. O hardware proposto foi desenvolvido em Field Programmable Gate Array (FPGA) utilizando ponto fixo. Todos os detalhes da arquitetura desenvolvida são apresentados, incluindo informações referentes à taxa de ocupação dos recursos de hardware, tempo de processamento e consumo energético para uma FPGA Stratix V 5SGXMBBR3H43C3. Através dos resultados obtidos, foi realizada uma análise comparativa do modelo obtido com outros trabalhos do estado da arte. Com isso, foi possível concluir que a implementação obteve um desempenho similar ou superior a outros trabalhos na literatura.

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Adaptive Boolean Logic Using Ferroelectrics Capacitors as Basic Units of Artificial Neurons and Its Implementation in FPGA

Cited by 2 publications

References 12 publications

Implementation three-step algorithm based on signed digit number system by using neural network

Implementation three-step algorithm based on signed digit number system by using neural network

Proposta de Implementação Paralela do Método Naive Bayes em FPGA

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