Adaptive coding technique employing concatenated Reed Solomon and convolutional codes

Soyjaudah, K. M. S.; Oolun, M.K.; Jahmeerbacus, I.; Bhurtun, C.

doi:10.1109/afrcon.2002.1146828

Cited by 4 publications

(2 citation statements)

References 10 publications

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“…In recent years, BCH-convolutional codes [3], a class of convolutional codes using a new parity-check matrix, is presented, which have many characteristics of BCH block codes and excellent free distance. RS-convolutional codes [4], employing concatenated reed solomon codes and convolutional codes, which employs the information available from the channel state estimator to vary the amount of redundancy and its error correcting capability according the state of the channel. LDPC-convolutional codes [5], Low-density parity-check (LDPC) convolutional codes, are capable of achieving excellent performance with low encoding and decoding complexity.…”

Section: Introductionmentioning

confidence: 99%

Design of (2, 1, N) Parallel Convolutional Encodes for VLSI

Duan

Huang

2013

AMM

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Abstract. The characters of more high speed computing and much less low power dissipation are needed to settle for convolutional encodes. In this paper, we present a parallel method for convolutional encodes with SMIC 0.35µm CMOS technology; hardware design and VLSI implementation of this algorithm are also presented. Use this method, parallel circuits structure can be easily designed, which take on excellent characters of more high speed computing and low power dissipation compared with traditional serial shift register structure for convolutional encodes.

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Section: Introductionmentioning

confidence: 99%

Design of (2, 1, N) Parallel Convolutional Encodes for VLSI

Duan

Huang

2013

AMM

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“…In recent years, BCH-convolutional codes [4], a class of convolutional codes using a new parity-check matrix, is presented, which have many characteristics of BCH block codes and excellent free distance. RS-convolutional codes [5], employing concatenated reed solomon codes and convolutional codes, which employs the information available from the channel state estimator to vary the amount of redundancy and its error correcting capability according the state of the channel. LDPC-convolutional codes [6], Low-density parity-check (LDPC) convolutional codes, are capable of achieving excellent performance with low encoding and decoding complexity.…”

Section: Introductionmentioning

confidence: 99%

IP Core Design for Parameterized (2,1,N) Convolutional Encodes

Duan

Huang

Yang

2013

AMM

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Abstract. In this paper, we design and implement general parameterized IP (Intellectual Property) cores of convolutional encoder with SMIC 0.35µm CMOS technology, serial structure and parallel structure respectively. And analyze each of the power dissipation using Synopsys PTPX tool. The result shows the parallel circuit structure saves 14 percent power dissipation compared to that of serial circuit structure, with the same encode radio. Meanwhile, computing speed of parallel structure with 8-bit parallelism is 8 times than that of serial structure under the same clock frequency. Certainly, serial circuit structure has their particular characters such as easily realized and less resource consumption.

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MWD Downhole Signal Transmission Boundary Condition Analysis and Wave Deconvolution

Bian

et al. 2011

2011 Third International Conference on Measuring Technology and Mechatronics Automation

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Adaptive coding technique employing concatenated Reed Solomon and convolutional codes

Cited by 4 publications

References 10 publications

Design of (2, 1, N) Parallel Convolutional Encodes for VLSI

Design of (2, 1, N) Parallel Convolutional Encodes for VLSI

IP Core Design for Parameterized (2,1,N) Convolutional Encodes

MWD Downhole Signal Transmission Boundary Condition Analysis and Wave Deconvolution

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