Adaptive Data Compression for Low-Power On-Chip Networks

Yan, Jin; Yum, Ki Hwan; Kim, Eun Jung

doi:10.1007/978-1-4419-6911-8_6

Cited by 6 publications

(18 citation statements)

References 27 publications

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“…Performance-wise, there are many existing router designs focusing on shortening the latency of a router [2]- [6], [12], [13]. There are also studies which focus on improving the bandwidth of NoCs through different approaches, such as compression [9], [10], allocators with higher matching efficiency [8], and different buffer designs allowing higher capacity [7]. Power-wise, there are many existing studies on saving the static power of routers through power management techniques such as PG [11] or proportionally supplying power to the network based on traffic demand [14].…”

Section: Related Workmentioning

confidence: 99%

“…Meanwhile, the static power of a router is reduced with PG and it is proportional to the amount of time when the router is switched on (T RouterOn i ) as in Eq. (10). N Router is the number of routers in a network.…”

Section: The Noc Optimization Techniques and Their Impactsmentioning

confidence: 99%

“…On NoCs, traffic compression is used to conserve bandwidth and to reduce packet latency [9], [10]. Additionally, it may help saving power since a successfully compressed packet may have its size shrunk, which can help saving dynamic power while the shrunk packet traverses the network.…”

Section: The Noc Optimization Techniques and Their Impactsmentioning

confidence: 99%

“…Advanced allocators try to increase the matching efficiency within a router [8]. Traffic compression aims to conserve network bandwidth and shorten propagation latency [9], [10]. Power gating is implemented for the routers to reduce their static power [11].…”

Section: Introductionmentioning

confidence: 99%

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A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip

Kondo

Nakada

et al. 2016

IEICE Trans. Inf. & Syst.

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SUMMARYNetworks-on-Chip (or NoCs, for short) play important roles in modern and future multi-core processors as they are highly related to both performance and power consumption of the entire chip. Up to date, many optimization techniques have been developed to improve NoC's bandwidth, latency and power consumption. But a clear answer to how energy efficiency is affected with these optimization techniques is yet to be found since each of these optimization techniques comes with its own benefits and overheads while there are also too many of them. Thus, here comes the problem of when and how such optimization techniques should be applied. In order to solve this problem, we build a runtime framework to throttle these optimization techniques based on concise performance and energy models. With the help of this framework, we can successfully establish adaptive selections over multiple optimization techniques to further improve performance or energy efficiency of the network at runtime.

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Section: Related Workmentioning

confidence: 99%

Section: The Noc Optimization Techniques and Their Impactsmentioning

confidence: 99%

Section: The Noc Optimization Techniques and Their Impactsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip

Kondo

Nakada

et al. 2016

IEICE Trans. Inf. & Syst.

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“…The wire propagation delay is linear with respect to the wire length. We assume each pipeline stage has a propagation delay of 183 ps per mm [38].…”

Section: B Modeling Memory Access Latencymentioning

confidence: 99%

GreenCool: An Energy-Efficient Liquid Cooling Design Technique for 3-D MPSoCs Via Channel Width Modulation

Sabry¹,

Sridhar²,

Meng

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Liquid cooling using interlayer microchannels has appeared as a viable and scalable packaging technology for 3-D multiprocessor system-on-chips (MPSoCs). Microchannelbased liquid cooling, however, can substantially increase the onchip thermal gradients, which are undesirable for reliability, performance, and cooling efficiency. In this paper, we present GreenCool, an optimal design methodology for liquid-cooled 3-D MPSoCs. GreenCool simultaneously minimizes the cooling energy for a given system while maintaining thermal gradients and peak temperatures under safe limits. This is accomplished by tuning the heat transfer characteristics of the microchannels using channel width modulation. Channel width modulation is compatible with the current process technologies and incurs minimal additional fabrication costs. Through an extensive set of experiments, we show that channel width modulation is capable of complementing and enhancing the benefits of temperatureaware floorplanning. We also experiment with a 16-core 3-D system with stacked dynamic random-access memory, for which GreenCool improves energy efficiency by up to 53% with respect to no channel modulation.

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Efficient Data Packet Compression for Cache Coherent Multiprocessor Systems

Lee

Yum

et al. 2012

2012 Data Compression Conference

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Multiprocessor systems have been popular for their high performance not only for server markets but also for computing environments for general users. With the increased software complexity, networking overheads in multiprocessor systems are becoming one of the most influential factors in overall system performance. In this paper, we attempt to reduce communication overheads through a data packet compression technique integrating a cache coherence protocol. Here we propose Variable Size Compression (VSC) scheme that compresses or completely eliminates data packets while harmonizing with existing cache coherence protocols. Simulation results show approximately 23% of improvement on average in terms of overall system performance when compared with the most recent compression scheme. VSC also improves performance by 20% on average in terms of cache miss latency. I. INTRODUCTIONWith the current trend in information technology, multiprocessor systems have been widely adopted to achieve better performance in diverse computing environments. Relying on traditional methods such as instruction-level parallelism (ILP) in uniprocessor environments has a limitation on performance improvement. Most software in recent days adopts multithread program structures, which were mainly used for high-performance computing environments exclusively. Under a high degree of parallelism, networking performance is getting more dominant than computation power in determining overall system performance. Since a traditional approach using shared buses is not a scalable solution, switch-based interconnection networks are regarded as a promising alternative in largescale multiprocessor systems. Providing an effective solution to reduce communication overheads has been one of the major goals in the multiprocessor system design.There has been plenty of research carried out to diminish overheads of interconnection networks in multiprocessor environments. This goal can be achieved in two ways: adopting a faster network with shorter latency and wider bandwidth, or decreasing the amount of network workloads. Some studies focus on the latter through data compression to reduce data packet overheads. Data compression used in memories and interconnects of multiprocessor systems helps to decrease the size of cache block data that is tranferred in the form of data packets through the network. Recently, a static data compression scheme [1] has been proposed to compresses data based on predefined fixed patterns, which fails to exploit dynamic communication behavior. To overcome this drawback, an adaptive compression scheme [2] uses tables containing frequently used patterns and updates them dynamically. However, both schemes simply reduce the packet size through compression and never attempt to incorporate the compression with underlying cache coherence protocols, which limits the amount of performance improvement at a certain level.This research tries to take a step forward to overcoming the limitation. Here we attempt to reduce communication overhe...

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Adaptive Data Compression for Low-Power On-Chip Networks

Cited by 6 publications

References 27 publications

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip

GreenCool: An Energy-Efficient Liquid Cooling Design Technique for 3-D MPSoCs Via Channel Width Modulation

Efficient Data Packet Compression for Cache Coherent Multiprocessor Systems

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