Adaptive data prefetching using cache information

Ki, Ando; Knowles, Alan E.

doi:10.1145/263580.263633

Cited by 13 publications

(4 citation statements)

References 6 publications

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“…A comprehensive survey of most popular prefetching schemes for multiprocessors (also applicable to uniprocessors) is presented in [27]. This survey paper discusses various prefetching schemes including pure hardware [2], [10], [4], [30], [11], software [5], [8], [19], [20], [15] and integrated schemes.…”

Section: Related Workmentioning

confidence: 99%

Adaptive prefetching for shared cache based chip multiprocessors

Kandemir

Zhang

Öztürk

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based CMP, multiple cores compete for the shared on-chip cache space and limited off-chip pin bandwidth. Purely software based prefetching techniques tend to increase this contention, leading to degradation in performance. In some cases, prefetches can become harmful by kicking out useful data from the shared cache whose next usage is earlier than the prefetched data, and the fraction of such harmful prefetches usually increases when we increase the number of cores used for executing a multi-threaded application code. In this paper, we propose two complementary techniques to address the problem of harmful prefetches in the context of shared L2 based CMPs. These techniques, namely, suppressing select data prefetches (if they are found to be harmful) and pinning select data in the L2 cache (if they are found to be frequent victim of harmful prefetches), are evaluated in this paper using two embedded application codes. Our experiments demonstrate that these two techniques are very effective in mitigating the impact of harmful prefetches, and as a result, we extract significant benefits from software prefetching even with large core counts.

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Section: Related Workmentioning

confidence: 99%

Adaptive prefetching for shared cache based chip multiprocessors

Kandemir

Zhang

Öztürk

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…We define a virtual resource that captures the expected efficiency of read-ahead [Revel et al 1997;Ki and Knowles 1997]. We build our metric of read-ahead confidence on the adaptive read-ahead logic recently introduced in the Linux kernel [Fengguang 2007].…”

Section: Calculating Resource Utilizationmentioning

confidence: 99%

Ca-NFS

Batsakis

Burns²,

Kanevsky

et al. 2009

ACM Trans. Storage

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We develop a holistic framework for adaptively scheduling asynchronous requests in distributed file systems. The system is holistic in that it manages all resources, including network bandwidth, server I/O, server CPU, and client and server memory utilization. It accelerates, defers, or cancels asynchronous requests in order to improve application-perceived performance directly. We employ congestion pricing via online auctions to coordinate the use of system resources by the file system clients so that they can detect shortages and adapt their resource usage. We implement our modifications in the Congestion-Aware Network File System (CA-NFS), an extension to the ubiquitous network file system (NFS). Our experimental result shows that CA-NFS results in a 20% improvement in execution times when compared with NFS for a variety of workloads.

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“…al [20] mitigate the negative effects of prefetching on performance by prefetching only when the memory bus is idle (to reduce contention), and prefetching to lower replacement priorities than demand misses (to reduce cache pollution). Ki and Knowles [31] used extra cache bits to increase prefetching's accuracy. Srinivasan, et.…”

Section: Related Workmentioning

confidence: 99%

Interactions Between Compression and Prefetching in Chip Multiprocessors

Alameldeen

Wood

2007

2007 IEEE 13th International Symposium on High Performance Computer Architecture

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In chip multiprocessors (CMPs), multiple cores compete for shared resources such as on-chip caches and off-chip pin bandwidth. Stride-based hardware prefetching increases demand for these resources, causing contention that can degrade performance (up to 35% for one of our benchmarks).In this paper, we first show that cache and link (off-chip interconnect) compression can increase the effective cache capacity (thereby reducing off-chip misses) and increase the effective off-chip bandwidth (reducing contention). On an 8-processor CMP with no prefetching, compression improves performance by up to 18%for commercial workloads. Second, we propose a simple adaptive prefetching mechanism that uses cache compressions extra tags to detect useless and harmful prefetches. Furthermore, in the central result of this paper, we show that compression and prefetching interact in a strong positive way, resulting in combined performance improvement of 10-51% for seven of our eight workloads.

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Adaptive data prefetching using cache information

Cited by 13 publications

References 6 publications

Adaptive prefetching for shared cache based chip multiprocessors

Adaptive prefetching for shared cache based chip multiprocessors

Ca-NFS

Interactions Between Compression and Prefetching in Chip Multiprocessors

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