Data prefetching that brings data close to the processor before it is actually used, can be done in parallel with computation, thus hiding the memory access latency and avoiding the need for the processor to stall. For maximum effectiveness it is necessary to adapt the prefetching parameters, such as prefetch offset and prefetch degree, to match programs and system conditions. Prefetch adaptability is the ability to change when to issue prefetching requests and the amount of data to be prefetched. We propose an adaptive mechanism of data prefetching using cache produced information, such as the usage of prefetched data and the rate of replacement of prefetched data. In this adaptive mechanism, the prefetch parameters are dynamically adjusted to reflect run-time variations of system behaviour. We use program driven simulation of scientific applications in the context of shared-memory multiprocessors to show that the proposed adaptive method can reduce memory access latency by reducing pending stall to a greater extent than can be achieved without an adaptive mechanism.

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A Cache coherence' protocols are important to operate a shared-memory multiprocessor system with efficiency and correctness. Cache coherence protocols become increasingly complex because physical memory is logically distributed so that it is difficult for programmers to understand the view of logical shared memory systems. Since random testing and simulations are not enough to validate correctness of protocols, it is necessary to develop eflcient and reliable verij2ation methods. Through the use of the Symbolic State Model by Fong

In thispapec we explore the design issues of a shared bus withpipelinedprotocol, so calledHiPi+Bus, which is implemented for a multiprocessor servex The characteristics and design parameters for the HiPi+Bus are described. In the viewpoint of apipelined bus, a block transfer is no good because of involving complex and unbalancedpipeline. Howeve? it is requested by a local cache memory of which line size tends to be increased. To get the best performance and compensate unbalanced data transfer characteristic caused by block transfer; a responder queue for the bus interface is also proposed. According to the simulation results, it is explored that the HiPi+Bus, with help of the responder queue, can provide balanced service for more than 16 processors, which is important in running commercial applications. The HtPi+Bus is implemented for the TICOM III, a successor of the TICOM II which is the main server of the national administrative information network in Korea.