Adaptive Latency-Insensitive Protocols

Casu, Mario R.; Macchiarulo, L.

doi:10.1109/mdt.2007.152

Cited by 19 publications

(14 citation statements)

References 8 publications

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“…Various implementations exist both in synchronous (e.g., [12]) and asynchronous (e.g., [1], [47]) circuits. Among the different implementations of anti-tokens, two main classes have been distinguished: passive anti-tokens, when they statically wait for the arrival of tokens, and active anti-tokens, when they move backward to meet tokens.…”

Section: A Early Evaluationmentioning

confidence: 99%

RTL Synthesis: From Logic Synthesis to Automatic Pipelining

Cortadella

Galceran-Oms²,

Kishinevsky

et al. 2015

Proc. IEEE

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Abstract-Design automation has been one of the main propellers of the semiconductor industry with logic synthesis being one of the core technologies in this field. The paper reviews the evolution of logic synthesis until the advent of techniques for automatic pipelining based on elastic timing, either synchronous or asynchronous. The emergence of these techniques can enable a productive interaction with tools that can do microarchitectural exploration of complex designs.

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Section: A Early Evaluationmentioning

confidence: 99%

RTL Synthesis: From Logic Synthesis to Automatic Pipelining

Cortadella

Galceran-Oms²,

Kishinevsky

et al. 2015

Proc. IEEE

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“…The FIC of each channel P i is stored in variable F IC P i (f , g), which is computed by the inner loop (lines 3-10). Then, F IC P i (f , g) is processed based on whether we want to generate the full set of FIC or only SDFIC, which depend only on state variables (lines [11][12][13][14]. The inner loop from lines 3 to 10 performs the main computation of FIC of channel P i .…”

Section: A Background Definitionsmentioning

confidence: 99%

“…The idea has been first investigated in the context of multiclock latency-insensitive circuits in [32] and [33], and it has been applied to elastic systems by using a new latency-insensitive protocol that explicitly encodes antitoken signals [34]. The work by Casu and Macchiarulo on adaptive latency-insensitive protocols [13] and our preliminary results on FIC-based optimization [18] have shown that unnecessary stalling can be avoided with local modification in the logic design of a shell and without requiring any change in the channel interface signals (void and stop bits) that were defined to implement the original latency-insensitive protocol [9].…”

Section: Related Workmentioning

confidence: 99%

“…Casu and Macchiarulo [13] identify the need to have an "effective and simple" combinational logic block, which they call "oracle," to implement the detection logic, but they do not provide a method to synthesize it. All the aforementioned approaches somewhat assume that the designers have full knowledge of the triggering conditions.…”

Section: ) Detection Logicmentioning

confidence: 99%

“…This notion is similar to the accumulation of negative tokens in the "guarded" Petri net model proposed by Júlvez et al [35] for performance analysis of early evaluation. Casu and Macchiarulo [13] implement this technique by using an up-down counter for each input channel whose value is the number of tokens to be discarded. We use a 1-bit shift register instead of an up-down counter to reduce the hardware overhead.…”

Section: ) Detection Logicmentioning

confidence: 99%

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Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip

Carloni

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Latency-insensitive design is a methodology for system-on-chip (SoC) design that simplifies the reuse of intellectual property cores and the implementation of the communication among them. This simplification is based on a system-level protocol that decouples the intracore logic design from the design of the intercore communication channels. Each core is encapsulated within a shell, a synthesized logic block that dynamically controls its operation to interface it with the rest of the SoC and absorb any latency variations on its I/O signals. In particular, a shell stalls a core whenever new valid data are not available on the input channels or a downlink core has requested a delay in the data production on the output channels. We study how knowledge about the internal logic structure of a core can be applied to the design of its shell to improve the overall system-level performance by avoiding unnecessary local stalling. We introduce the notion of functional independence condition (FIC) and present a novel circuit design of a generic shell template that can leverage FIC. We propose a procedure for the logic synthesis of a FIC-shell instance that is only based on the analysis of the intracore logic and does not require any input from the designers. Finally, we present a comprehensive experimental analysis that shows the performance benefits and limited design overhead of the proposed technique. This includes the semicustom design of an SoC, an ultrawideband baseband transmitter, using a 90-nm industrial standard cell library.Index Terms-Finite state machines (FSMs), latency-insensitive design (LID), logic synthesis, sequential logic optimization, system-level design, system-on-chip (SoCs).

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