RTL Synthesis: From Logic Synthesis to Automatic Pipelining

Cortadella, Jordi; Galceran-Oms, Marc; Kishinevsky, Michael; Sapatnekar, Sachin S.

doi:10.1109/jproc.2015.2456189

Cited by 12 publications

(5 citation statements)

References 45 publications

(54 reference statements)

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“…The DPSO algorithm was used for the timing optimization of 17 MPRM logic circuits. The same combinational logic circuit was operated independently 20 times, and the timing of the optimized combinational logic circuit was calculated according to (4). Then, the DC algorithm was used for timing constraint and for setting the same MCNC benchmark circuits to ensure that the logic gates covered in the netlist after logic synthesis are completely consistent with the logic gates in the MPRM circuits.…”

Section: Results Analysis and Discussionmentioning

confidence: 99%

“…MCNC benchmark circuits were used as the MPRM circuit in the verification process. First, the DPSO algorithm was used for timing optimization of the MCNC benchmark circuit, and an equivalent timing was calculated according to (4). Second, the format of the MCNC benchmark circuit was modified.…”

Section: Verification Methodmentioning

confidence: 99%

“…Timing optimization for logic circuits is one of the most important requirements during logic synthesis [1][2][3][4]. The industry's mainstream electronic design automation (EDA) tool for logic synthesis is Design Compiler (DC) produced by Synopsys5.…”

Section: Introductionmentioning

confidence: 99%

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Novel Verification Method for Timing Optimization Based on DPSO

et al. 2018

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Timing optimization for logic circuits is one of the key steps in logic synthesis. Extant research data are mainly proposed based on various intelligence algorithms. Hence, they are neither comparable with timing optimization data collected by the mainstream electronic design automation (EDA) tool nor able to verify the superiority of intelligence algorithms to the EDA tool in terms of optimization ability. To address these shortcomings, a novel verification method is proposed in this study. First, a discrete particle swarm optimization (DPSO) algorithm was applied to optimize the timing of the mixed polarity Reed-Muller (MPRM) logic circuit. Second, the Design Compiler (DC) algorithm was used to optimize the timing of the same MPRM logic circuit through special settings and constraints. Finally, the timing optimization results of the two algorithms were compared based on MCNC benchmark circuits. The timing optimization results obtained using DPSO are compared with those obtained from DC, and DPSO demonstrates an average reduction of 9.7% in the timing delays of critical paths for a number of MCNC benchmark circuits. The proposed verification method directly ascertains whether the intelligence algorithm has a better timing optimization ability than DC.

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Section: Results Analysis and Discussionmentioning

confidence: 99%

Section: Verification Methodmentioning

confidence: 99%

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Novel Verification Method for Timing Optimization Based on DPSO

et al. 2018

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“…The following conditions are necessary to ensure deadlockfree execution of dataflow systems: (1) Each combinational cycle must be broken with at least one nontransparent buffer; this requirement is analogous to that in standard synchronous circuits, where each combinational cycle needs to be broken using a register, and (2) each cycle in must contain at least one token and one bubble [16]; this requirement ensures that a token and a bubble can always exchange places and tokens can with a single buffer slot will cause deadlock, as the token will not be able to propagate through the cycle. At least two buffer slots are necessary to ensure deadlock-free execution.…”

Section: Buffers and Avoiding Deadlockmentioning

confidence: 99%

From C/C++ Code to High-Performance Dataflow Circuits

Josipović

Guerrieri

Ienne

2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where performance is limited by long latency control decisions. In this work, we describe an HLS approach which generates dynamically scheduled, dataflow circuits out of imperative code. We detail a complete set of rules to transform a standard compiler intermediate representation into a high-performance dataflow circuit that is able to dynamically resolve memory dependences and adapt its behavior on the fly to particular control flow decisions and operation latencies. Compared to a traditional HLS tool, the result is a different trade-off between performance and circuit complexity: statically scheduled circuits display the best performance per cost in regular applications, but general-purpose, irregular, and control-dominated computing tasks require the runtime flexibility of dynamic scheduling. Therefore, enabling dynamic behavior in HLS is key to dealing with the increasing computational demands of new contexts and broader application domains.

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“…Fig. 1 shows the pipelining design of a digital integrated circuit [1]. The combinational logic circuit between triggers is represented by ellipses.…”

Section: Introductionmentioning

confidence: 99%

Verification Method for Area Optimization of Mixed-Polarity Reed-Muller Logic Circuits

Chen

Lin

Zhu³

2018

JESTR

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Area minimization of mixed-polarity Reed-Muller (MPRM) logic circuits is an important step in logic synthesis. While previous studies are mainly based on various artificial intelligence algorithms and not comparable with the results from the mainstream electronics design automation (EDA) tool. Furthermore, it is hard to verify the superiority of intelligence algorithms to the EDA tool on area optimization. To address these problems, a multi-step novel verification method was proposed. First, a hybrid simulated annealing (SA) and discrete particle swarm optimization (DPSO) approach (SADPSO) was applied to optimize the area of the MPRM logic circuit. Second, a Design Compiler (DC) algorithm was used to optimize the area of the same MPRM logic circuit under certain settings and constraints. Finally, the area optimization results of the two algorithms were compared based on MCNC benchmark circuits. Results demonstrate that the SADPSO algorithm outperforms the DC algorithm in the area optimization for MPRM logic circuits. The SADPSO algorithm saves approximately 9.1% equivalent logic gates compared with the DC algorithm. Our proposed verification method illustrates the efficacy of the intelligence algorithm in area optimization compared with DC algorithm. Conclusions in this study provide guidance for the improvement of EDA tools in relation to the area optimization of combinational logic circuits.

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RTL Synthesis: From Logic Synthesis to Automatic Pipelining

Cited by 12 publications

References 45 publications

Novel Verification Method for Timing Optimization Based on DPSO

Novel Verification Method for Timing Optimization Based on DPSO

From C/C++ Code to High-Performance Dataflow Circuits

Verification Method for Area Optimization of Mixed-Polarity Reed-Muller Logic Circuits

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