Adaptive Layout Technique for Microhybrid Integration of Chip-Film Patch

Alavi, Golzar; Sailer, Holger; Albrecht, Björn; Harendt, Christine; Burghartz, Joachim N.

doi:10.1109/tcpmt.2018.2818762

Cited by 23 publications

(10 citation statements)

References 10 publications

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“…9b) and the adjusted layout is applied lithographically (Fig. 9c) [20], [21]. This adaptive layout technique, thus, provides a means of taking full advantage of the CFP concept.…”

Section: A Chip-film Patch (Cfp) Embedding Technologymentioning

confidence: 99%

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Hybrid Systems-in-Foil—Combining the Merits of Thin Chips and of Large-Area Electronics

Burghartz

Alavi

Albrecht

et al. 2019

IEEE J. Electron Devices Soc.

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This paper reports on the status of a comprehensive ten-year research and development effort toward hybrid system-in-foil (HySiF). In HySiF, the merits of high-performance integrated circuits on ultra-thin chips and of large-area and discrete electronic component implementation are combined in a complementary fashion in and on a flexible carrier substrate. HySiF paves the way to entirely new applications of electronic products where form factor, form adaptivity and form flexibility are key enablers. In this review paper the various aspects of thin-chip fabrication and embedding, device and circuit design under impact of unknown or variable mechanical stress, and the on-and off-chip implementation of sensor, actuator, microwave, and energy supply components are addressed. INDEX TERMS Hybrid integrated circuits, thin film circuits, flexible electronics, micro assembly, multichip modules, chip scale packaging.

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“…9b) and the adjusted layout is applied lithographically (Fig. 9c) [20], [21]. This adaptive layout technique, thus, provides a means of taking full advantage of the CFP concept.…”

Section: A Chip-film Patch (Cfp) Embedding Technologymentioning

confidence: 99%

“…It can also be instrumental in applying layout adjustments to global interconnects on thin and embedded chips due to chip warpage. Economic constraints of laser lithography can be addressed by exploiting mix&match lithography [20], [21].…”

Section: A Chip-film Patch (Cfp) Embedding Technologymentioning

confidence: 99%

Hybrid Systems-in-Foil—Combining the Merits of Thin Chips and of Large-Area Electronics

Burghartz

Alavi

Albrecht

et al. 2019

IEEE J. Electron Devices Soc.

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“…With the help of the adaptive layout technology, the initial interconnect layout between the embedded chips in the polymer foil is adopted based on the calculated rotation and misalignment of the embedded chips in the polymer foil using direct laser writer lithography tool [11,17].…”

Section: Two-polymer Cfp Technologymentioning

confidence: 99%

Toward a flexible and adaptive wireless hub by embedding power amplifier thinned silicon chip and antenna in a polymer foil

Alavi

Özbek

Rasteh

et al. 2019

Int. J. Microw. Wireless Technol.

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A flexible and adaptive energy-efficient high-speed wireless hub is developed in polymer foil as a Hybrid System-in-Foil (HySiF) using Chip-Film Patch (CFP) technology. In this matter, the SiGe BiCMOS silicon chips (2.39 × 1.65 mm2) are thinned down to 45 μm and are embedded face-up inside a two-polymer CFP carrier. The active pads of the embedded silicon chips inside foil are extended to the surface of the foil to interconnect to the antenna on the foil. The integrated hybrid system has a signal transmission at 5–6 GHz frequency band. The overall thickness of the system is below 100 μm and its bendability is down to 4 mm radius of curvature. The designed and fabricated PA silicon chips operate at 50 mA with a 1.5 V supply voltage. Therefore, in addition to the high lateral thermal resistance of the thinned chip, self-heating loop inside polymer due to the low thermal conductivity of the embedding polymer raises the system temperature. Consequently, the thermal behavior and RF performance of the PA chip under different conditions are investigated. Moreover, the antenna with the required carrier frequency is simulated, fabricated, and measured on top of the polymer foil as a stand-alone system in the flexible CFP.

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“…After silicon thinning, the chips are detached from the wafer release foil and assembled either by face-down flip-chip technology [ 9 , 10 , 11 ] or face-up die-bonding with subsequent electrical contacting [ 12 , 13 , 14 , 15 ]. There are various disadvantages of flip-chip assembly in regard to ultrathin chips.…”

Section: Introductionmentioning

confidence: 99%

Feasibility Study of an Automated Assembly Process for Ultrathin Chips

et al. 2020

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This paper presents a feasibility study of an automated pick-and-place process for ultrathin chips on a standard automatic assembly machine. So far, scientific research about automated assembly of ultrathin chips, with thicknesses less than 50 µm, is missing, but is necessary for cost-effective, high-quantity production of system-in-foil for applications in narrow spaces or flexible smart health systems applied in biomedical applications. Novel pick-and-place tools for ultrathin chip handling were fabricated and a process for chip detachment from thermal release foil was developed. On this basis, an adhesive bonding process for ultrathin chips with 30 µm thickness was developed and transferred to an automatic assembly machine. Multiple ultrathin chips aligned to each other were automatically placed and transferred onto glass and polyimide foil with a relative placement accuracy of ±25 µm.

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Adaptive Layout Technique for Microhybrid Integration of Chip-Film Patch

Cited by 23 publications

References 10 publications

Hybrid Systems-in-Foil—Combining the Merits of Thin Chips and of Large-Area Electronics

Hybrid Systems-in-Foil—Combining the Merits of Thin Chips and of Large-Area Electronics

Toward a flexible and adaptive wireless hub by embedding power amplifier thinned silicon chip and antenna in a polymer foil

Feasibility Study of an Automated Assembly Process for Ultrathin Chips

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