Adaptive Low Power RTPG for BIST based test applications

John, Renju Thomas; Sreekanth, K D; Sivanantham, S.

doi:10.1109/icices.2013.6508185

Cited by 5 publications

(5 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…al. [1] Proposed an Adaptive Low Power RTPG for BIST based test applications. In this research paper, researcher reduction during testing in scan based tests.…”

Section: Otivation Of Researchmentioning

confidence: 99%

“…al. [1] Discussed about An Efficient Parallel Transparent BIST Method for Multiple Embedded Memory Buffers. In this paper, researchers proposed a new transparent builtin self-test (T-BIST) technique to test multiple embedded memory arrays with various sizes in parallel.…”

Section: Otivation Of Researchmentioning

confidence: 99%

“…Therefore, to perform the test, the normal operation of the CUT is inhibited and, consequently, the performance of the system in which the circuit is turned on is deteriorating. [1] To exclude this performance degradation, parallel BIST methods were proposed that use input vectors fed to the CUT inputs during normal operation.BIST uses a test pattern generator (TPG) to generate test patterns that apply to the inputs of the tested circuit (CUT). The block diagram of the input vector controlling the parallel BIST technology is shown in Figure. 1.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Built in Self Test Architecture Using Logic Module

Shrivastava¹,

Malviya²,

Gupta³

2017

VLSICS

View full text Add to dashboard Cite

show abstract

“…al. [1] Proposed an Adaptive Low Power RTPG for BIST based test applications. In this research paper, researcher reduction during testing in scan based tests.…”

Section: Otivation Of Researchmentioning

confidence: 99%

Section: Otivation Of Researchmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Built in Self Test Architecture Using Logic Module

Shrivastava¹,

Malviya²,

Gupta³

2017

VLSICS

View full text Add to dashboard Cite

show abstract

“…A lot of methods had been proposed for this, for instance, a low hardware overhead test pattern generator for scanbased BIST was discussed [16], the generator can decrease the transitions that occur at scan inputs during scan shift operations, therefore can reduce the switching activity in the circuits under test. The adaptive low power random test pattern generator was discussed [17], which can improve the tradeoff between shift power reduction and the test coverage, the generator made that the previous test responses were given as feedback to a transition controller. A low power BIST architecture using pattern mapping strategy was investigated [18], the architecture made use of transition freezing approach that produces the frozen patterns according to the transition tendency of a linear feedback shift registers (LFSR), therefore the BIST architecture can get the average power reduction.…”

Section: Introductionmentioning

confidence: 99%

Test Pattern Generation with Low Power for Delay Faults in Digital Circuits by Evolution Method with Hybrid Strategies

Zhang

Ling²,

Chen³

2014

TOEEJ

View full text Add to dashboard Cite

The high power consumption during circuit test process can produce unwanted failures or take effects on circuit reliability, therefore the reduction of both peak power and average power of circuit test is necessary. A test pattern generation approach is presented in this paper for the delay faults in digital circuits, the approach makes use of the evolution method with the hybrid strategies to produce the test vectors with low power consumption. First of all, a pair of vectors that may detect a delay fault is coded as an individual. A lot of individuals constitute the populations. Secondly, the test vectors with low power are produced by the evolution of these populations. Many new individuals are randomly produced and are added into every evolution step, and the mutation mode of individuals is related to other individuals in the current population. A lot of experimental results show that the test vectors with low power for the delay faults in digital circuits can be produced by the approach proposed in this paper, and the approach can get the large reduction of power consumption when compared with random test generation algorithm.

show abstract

“…In case of offline BIST chip is not in normal operation. The requirement of efficient and economical testing method such as the Built-In Self-Test (BIST) increases with the increase in complexity of Very Large Scale Integration (VLSI) devices or System-on-Chip (SoC) [2]. The logic behind BIST is to design an IC that is capable of verifying itself as being either fault-free or faulty and then continue its operation when the testing is not being carried out.…”

Section: Introductionmentioning

confidence: 99%