Adaptive Shared Memory Control for Multimedia Systems-on-Chip

Abstract

Memory subsystem is a major concern in the design of multimedia systems and the memory performance may become the bottleneck for the overall processing performance. This work presents a memory subsystem implementation with adaptive control for access to shared memory in multimedia Systems-on-Chip (SoC). A memory-centric design approach is used to implement the memory subsystem for the purpose of meet bandwidth and deadline requirements of the heterogeneous processing elements. A latency-based model is obtained based on the Worst-Case Response Time (WCRT) criterion. In the presented approach, an adaptive arbiter is designed and implemented to control memory access requests targeting to comply with clients' deadline requirements managing data latency of accesses. Also, an algorithmic implementation of the adaptive arbitration control is presented and evaluated. This paper presents hardware implementation results for the proposed memory subsystem with an adaptive arbiter control. Our proposal of simple estimation of WCRT leads to a hardware implementation with low latency calculation of the system limits imposed to clients. This way the proposed adaptation approach can be implemented at run-time.