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This work presents the integration of several IPs to generate a system-on-chip (SoC) for digital television set-top box compliant to the SBTVD standard. Embedded consumer electronics for multimedia applications like video processing systems require large storage capacity and high bandwidth memory. Also, those systems are built from heterogeneous processing units, designed to perform specific tasks in order to maximize the overall system efficiency. A single off-chip memory is generally shared between the processing units to reduce power and save costs. The external memory access is one bottleneck when decoding high-definition video sequences in real time. In this work, a four-level memory hierarchy was designed to manage the decoded video in macroblock granularity with low latency. The use of the memory hierarchy in the system design is challenging because it impacts the system integration process and IP reuse in a collaborative design team. Practical strategies used to solve integration problems are discussed in this text. The SoC architecture was validated and is being progressively prototyped using a Xilinx Virtex-5 FPGA board.

Embedded consumer electronics like video processing systems require large storage capacity and high bandwidth memory access. Also, those systems are built from heterogeneous processing units, designed specifically to perform dedicated tasks in order to maximize the processing efficiency. A single off-chip memory is shared between the processing units to reduce power and save costs. The external memory access is the system bottleneck when decoding high definition video sequences in real time. A fourlevel memory hierarchy was designed to manage the decoded video in macroblock granularity with low latency. The inclusion of the memory hierarchy in the system has also implications on system integration and IP reuse in a collaborative design. This work presents some issues in the integration of the memory hierarchy on the system and practical strategies used to solve them. This architecture was validated and is being progressively prototyped using a Xilinx Virtex-5 FPGA board.