Run-time SoC memory subsystem mapping of heterogeneous clients

Bonatto, Alexsandro Cristóvão; Susin, Altamiro

doi:10.1109/iscas.2014.6865201

Cited by 1 publication

(4 citation statements)

References 7 publications

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“…Combining equations (1), (2) and (3) leads to a measure in clock cycles of the time spent to transfer a set of data in the memory subsystem. Different combinations of elements can be formed to implement a memory subsystem, but in the present case we use an architectural implementation as proposed in Fig.…”

Section: Worst-case Response Timementioning

confidence: 99%

“…The choice of transfer granularity (g) influences on the overall system performance as presented in [2]. The preemption of an ongoing transaction regarding a minimum granularity size leads to the minimization of data latency across the memory subsystem to complete requests that are processed by the memory controller and increase data bandwidth for the client that is preempted.…”

Section: Worst-case Response Timementioning

confidence: 99%

“…The preemption of an ongoing transaction regarding a minimum granularity size leads to the minimization of data latency across the memory subsystem to complete requests that are processed by the memory controller and increase data bandwidth for the client that is preempted. As proposed in [2], an optimal value of granularity can be selected by the arbiter to preempt clients. In this implementation, we will make gn = ln/2, that leads to a simplification of the architectural implementation.…”

Section: Worst-case Response Timementioning

confidence: 99%

“…Because processing elements can have a timing variant data access behavior, adaptive priorities control and client access preemption for memory access has benefits to the memory subsystem, as presented before in [8,6]. Memory system model and design are widely explored in recent works [1,2,7,8,6,12,3,4,15,16,17] and show the state-of-the-art in the area of memory systems design.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Adaptive Shared Memory Control for Multimedia Systems-on-Chip

Bonatto

Negreiros

Pereira

et al. 2014

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design

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Memory subsystem is a major concern in the design of multimedia systems and the memory performance may become the bottleneck for the overall processing performance. This work presents a memory subsystem implementation with adaptive control for access to shared memory in multimedia Systems-on-Chip (SoC). A memory-centric design approach is used to implement the memory subsystem for the purpose of meet bandwidth and deadline requirements of the heterogeneous processing elements. A latency-based model is obtained based on the Worst-Case Response Time (WCRT) criterion. In the presented approach, an adaptive arbiter is designed and implemented to control memory access requests targeting to comply with clients' deadline requirements managing data latency of accesses. Also, an algorithmic implementation of the adaptive arbitration control is presented and evaluated. This paper presents hardware implementation results for the proposed memory subsystem with an adaptive arbiter control. Our proposal of simple estimation of WCRT leads to a hardware implementation with low latency calculation of the system limits imposed to clients. This way the proposed adaptation approach can be implemented at run-time.

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Section: Worst-case Response Timementioning

confidence: 99%

Section: Worst-case Response Timementioning

confidence: 99%

Section: Worst-case Response Timementioning

confidence: 99%