Adaptive techniques for overcoming performance degradation due to aging in digital circuits

Kumar, Vivek; Sapatnekar, Sachin S.

doi:10.1109/aspdac.2009.4796494

Cited by 57 publications

(21 citation statements)

References 20 publications

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“…Adaptive voltage scaling (AVS) is a design technique that compensates for BTI-induced circuit performance degradation by increasing the supply voltage of a circuit [2], [15], Manuscript [27]. Since supply voltage is increased to compensate for BTI-induced timing degradation, the supply voltage of the circuit at the end of lifetime is higher than the supply voltage at the beginning of lifetime .…”

Section: Introductionmentioning

confidence: 99%

On Aging-Aware Signoff for Circuits With Adaptive Voltage Scaling

Chan

Kahng

2014

IEEE Trans. Circuits Syst. I

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Abstract-Transistor aging due to bias temperature instability (BTI) is a major reliability concern in sub-32 nm technology. To compensate for aging, designs now typically apply adaptive voltage scaling (AVS) to mitigate performance degradation by elevating supply voltage. Since varying the supply voltage also causes the BTI degradation to vary over lifetime, this presents a new challenge for margin reduction in the context of conventional signoff methodology, which characterizes timing libraries based on transistor models with pre-calculated BTI degradations for a given IC lifetime. In this paper, we study the conditions under which a circuit with AVS requires additional timing margin during signoff. Then, we propose two heuristics for chip designers to characterize an aging-derated standard-cell timing library that accounts for the impact of AVS during signoff. According to our experimental results, this aging-aware signoff approach avoids both overestimation and underestimation of aging-either of which results in power or area penalty-in AVS-enabled systems. Further, we compare circuits implemented with the aging-aware signoff method based on aging-derated libraries versus those based on a flat timing margin. We demonstrate that the flat timing margin method is more pessimistic, and that the pessimism can be mitigated by AVS.

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Section: Introductionmentioning

confidence: 99%

On Aging-Aware Signoff for Circuits With Adaptive Voltage Scaling

Chan

Kahng

2014

IEEE Trans. Circuits Syst. I

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“…This paper outperforms all state-of-the-art approaches. As a comparison point, approaches in [24], [44], and [45] recover only 15-32% of OWG LCPE degradation for worst-case aging, while PWCA, POSA, and PRTA recover 52%, 83%, and 93% of OWG LCPE degradation, respectively.…”

Section: F Interactions With Process Variationsmentioning

confidence: 99%

“…Reference [24] gradually increased supply voltage over lifetime to compensate for aging effects. Reference [45] pre-determined several tuningtimes and then at each tuning-time enumerated to decide bodybias and supply voltage values to compensate for worst-case aging effects. However, the aforementioned schemes in the previous work still have some limitations hence suboptimal, i.e., did not find the optimal tuning assignments.…”

Section: F Interactions With Process Variationsmentioning

confidence: 99%

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Mintarno

Skaf

Zheng

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper presents an integrated framework, together with control policies, for optimizing dynamic control of self-tuning parameters of a digital system over its lifetime in the presence of circuit aging. A variety of self-tuning parameters such as supply voltage, operating clock frequency, and dynamic cooling are considered, and jointly optimized using efficient algorithms described in this paper. Our optimized self-tuning approach satisfies performance constraints at all times, and maximizes a lifetime computational power efficiency (LCPE) metric, which is defined as the total number of clock cycles achieved over lifetime divided by the total energy consumed over lifetime. We present three control policies: 1) progressive-worst-case-aging (PWCA), which assumes worst-case aging at all times; 2) progressive-on-stateaging (POSA), which estimates aging by tracking active/sleep modes, and then assumes worst-case aging in active mode and long recovery effects in sleep mode; and 3) progressive-real-timeaging-assisted (PRTA), which acquires real-time information and initiates optimized control actions. Various flavors of these control policies for systems with dynamic voltage and frequency scaling (DVFS) are also analyzed. Simulation results on benchmark circuits, using aging models validated by 45 nm measurements, demonstrate the effectiveness and practicality of our approach in significantly improving LCPE and/or lifetime compared to traditional one-time worst-case guardbanding. We also derive system design guidelines to maximize self-tuning benefits.Index Terms-Adaptive supply voltage and clock frequency, circuit aging, energy-efficiency, lifetime reliability.

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“…At isoperformance, this results in lower aging, which translates to power savings through reduced delay margining, as compared to conventional design. Static presilicon [18] or adaptive postsilicon [19,20] techniques may also be used to pad the circuit against BTI degradation based on time sensors, history sensors that track usage patterns, or surrogate sensor circuits. Optimization knobs include changing the supply voltages, body biases, or both, using using dynamic cooling, and through redundancy and disposable cores.…”

Section: Circuit Optimizationmentioning

confidence: 99%

What happens when circuits grow old: Aging issues in CMOS design

Sapatnekar¹

2013

2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)

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As CMOS technologies have shrunk to tens of nanometers, aging problems have emerged as a major challenge. There has been tremendous progress in developing new methods for modeling and diagnosing reliability at the level of individual transistors, but much less work on propagating these models to higher levels of abstraction to analyze and optimize the reliability of larger circuits. This talk will provide an introduction to various circuit aging mechanisms and will then discuss research that develops computer-aided design techniques for estimating and enhancing the reliability of large digital circuits, examining solutions that could practically be applied to analyze or improve the lifetime of a design while maintaining consistency to accurate device-level models and the associated physics.CIRCUIT-LEVEL ANALYSIS OF AGING Aging effects are described by the classical bathtub curve: after a steep initial failure rate, the failures level off for a while before rising again, resulting in a bathtub-like shape for the number of failures as a function of time. Aging is strongly sensitivity to process parameter variations, as well as to onchip temperature and supply voltage level changes. Here, we overview analysis methods for prominent aging mechanisms, based on both conventional and newer physical models. Bias temperature instability (BTI) is a device aging phenomenon that causes threshold voltage shifts over long periods of time in the presence of voltage stress at the gate, eventually causing the circuit to fail to meet its specifications. A PMOS transistor in an inverter experiences negative BTI stress when its gate node is at logic 0, and the resulting increase in the threshold voltage is partially reversed when the voltage stress is removed (i.e., a logic 1 is applied). A similar phenomenon of positive BTI affects the threshold voltage of NMOS devices when they are stressed, and relaxes the degradation on the removal of stress. The magnitude of degradation depends on the ratio of the stressed time to unstressed time, i.e., the signal probability (SP) of the gate input. There are two widely-used theories for BTI. The reaction-diffusion (R-D) model [1,2] explains the degradation due to the accumulation of positive charges as Si-H bonds at the interface are broken and hydrogen diffuses away; the removal of this stress allows partial restoration of these bonds. The charge-trapping (CT) model [3] provides an alternative explanation, where defects in gate dielectrics can capture charged carriers, causing the threshold voltage to degrade. Neither theory fully explains experimental observations, and it has been posited that R-D and CT mechanisms coexist. The CT model predicts high variability in small devices, making variability a major factor for memories. For logic circuits, however, large transistors and averaging effects on critical paths significantly mitigate variability [4]. Hot carrier injection (HCI) in MOSFETs is caused by the acceleration of carriers (electrons/holes) under lateral electric fields in th...

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Adaptive techniques for overcoming performance degradation due to aging in digital circuits

Cited by 57 publications

References 20 publications

On Aging-Aware Signoff for Circuits With Adaptive Voltage Scaling

On Aging-Aware Signoff for Circuits With Adaptive Voltage Scaling

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

What happens when circuits grow old: Aging issues in CMOS design

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