ADC integral non-linearity testing with low linearity monotonic signals

Vasan, Bharath K; Chen, Degang J.; Geiger, R.L.

doi:10.1109/imtc.2011.5944342

Cited by 5 publications

References 11 publications

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A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC

Kerzérho

Bernard

Azaïs

et al. 2013

Microelectronics Journal

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The histogram-based technique is commonly used for testing of Analog-to-Digital Converters (ADC). One of the parameters measured thanks to this technique is the Integral Non Linearity (INL). INL is also used as an initial data related to the ADC performances for the computation of a correction table in case of a LUT-based correction technique. In this context of embedded INL measurement and embedded computation of the table for LUT-based correction of ADC, we propose a new implementation establishing what we consider the best trade-off between silicon area overhead and computing time. We compare our solution with the state of the art: (a) with VHDL-level simulation we compare time performance, and (b) with FPGA placer we estimate the final surface head-out.

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A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC

Kerzérho

Bernard

Azaïs

et al. 2013

Microelectronics Journal

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On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test

Renaud

Barragán

Mir

et al. 2014

2014 IEEE 23rd Asian Test Symposium

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International audienceLinearity testing for ADCs is one of the most resource and time consuming tasks in the production test of a mixed-signal integrated system. Advanced strategies for reducing static test time, such as the reduced code linearity test technique, have been recently presented. However, the application of these techniques require a high linearity input stimulus to excite the ADC under test, which is usually provided by an external analog signal generator in the ATE. Extending the static linearity test to a BIST implementation requires to include this generator on-chip, which is a challenging task. This paper explores different possibilities for the on-chip implementation of such generators

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ADC test methods using an impure stimulus: A survey

Schat

2018

2018 IEEE 23rd European Test Symposium (ETS)

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ADC integral non-linearity testing with low linearity monotonic signals

Cited by 5 publications

References 11 publications

A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC

A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC

On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test

ADC test methods using an impure stimulus: A survey

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