On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test

Abstract

International audienceLinearity testing for ADCs is one of the most resource and time consuming tasks in the production test of a mixed-signal integrated system. Advanced strategies for reducing static test time, such as the reduced code linearity test technique, have been recently presented. However, the application of these techniques require a high linearity input stimulus to excite the ADC under test, which is usually provided by an external analog signal generator in the ATE. Extending the static linearity test to a BIST implementation requires to include this generator on-chip, which is a challenging task. This paper explores different possibilities for the on-chip implementation of such generators

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs

“…The proposed ramp generation technique, originally described in [21] and further developed in [20], is based on a two-input switched-capacitor (SC) integrator with a small capacitance difference in its input sampling capacitors, C i1 and C i2 . Fig.…”

Design of an on-chip stepwise ramp generator for ADC static BIST applications

“…In this work, our goal is to design a ramp generator using simple circuitry, compatible with the technique proposed by the authors in [1] and reduced code testing techniques. Our proposal is based on a discrete-time SC integrator with a 978-1-4673-6732-5/15/$31.00 c 2015 IEEE very small integration gain.…”

“…The proposed generation technique, firstly described by the authors in [1], is based on a two-input SC integrator with a small capacitance difference in its input sampling capacitors. Figure 1 shows the schematic of the proposed generator.…”

“…The core of the proposed ramp generator is a fully-differential parasitic-insensitive switched-capacitor integrator that operates with two non-overlapping clock phases, φ 1 and φ 2 . Digital control signals φ up and φ down allow to control the sign of the ramp slope for each integration step, signal φ reset performs a reset of the integrating capacitor, and signal φ 0 is added to charge the output of the integrator to a reference voltage V a for measurement calibration purposes [1].…”

“…This proposal is to be implemented in an integratorbased servo-loop BIST technique previously described in [1], aimed at locating the transition voltages for a selected set of target codes, and enabling the use of reduced code linearity test techniques [2], [3].…”