Addressing key challenges in 1T-DRAM: Retention time, scaling and variability &amp;#x2014; Using a novel design with GaP source-drain

Pal, Ashish; Nainani, Aneesh; Saraswat, Krishna C.

doi:10.1109/sispad.2013.6650653

Cited by 3 publications

(1 citation statement)

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“…When millions of the 1T DRAM cells are integrated within a single array, the variation in the cell leads to data corruption during the memory operation. The 1T DRAM array should guarantee at least 98% of cells enable to work despite the device variability for its normal operation [ 22 ]. Aggressively scaled FBFETs suffer from random dopant fluctuation, causing device-to-device variation.…”

Section: Introductionmentioning

confidence: 99%

Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors

2023

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Challenges in scaling dynamic random-access memory (DRAM) have become a crucial problem for implementing high-density and high-performance memory devices. Feedback field-effect transistors (FBFETs) have great potential to overcome the scaling challenges because of their one-transistor (1T) memory behaviors with a capacitorless structure. Although FBFETs have been studied as 1T memory devices, the reliability in an array must be evaluated. Cell reliability is closely related to device malfunction. Hence, in this study, we propose a 1T DRAM consisting of an FBFET with a p+–n–p–n+ silicon nanowire and investigate the memory operation and disturbance in a 3 × 3 array structure through mixed-mode simulations. The 1T DRAM exhibits a write speed of 2.5 ns, a sense margin of 90 μA/μm, and a retention time of approximately 1 s. Moreover, the energy consumption is 5.0 × 10−15 J/bit for the write ‘1’ operation and 0 J/bit for the hold operation. Furthermore, the 1T DRAM shows nondestructive read characteristics, reliable 3 × 3 array operation without any write disturbance, and feasibility in a massive array with an access time of a few nanoseconds.

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Section: Introductionmentioning

confidence: 99%