Addressing thermal and power delivery bottlenecks in 3D circuits

Sapatnekar, Sachin S.

doi:10.1109/aspdac.2009.4796518

Cited by 32 publications

(13 citation statements)

References 23 publications

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“…For a 3D chip with a footprint size of 1cm 2 , we may have thousands of P/G I/Os for each die and millions of wire segments on the P/G grids in each die [2]. The enhanced packing densities facilitated by 3D integrated circuit technology also have an unwanted side-effect, in the form of increasing the amount of current per unit footprint of the chip, as compared to a 2D design [3]. From the experimental results it is observed that a single TSV failure could increase the maximum voltage variation up to 70% in nano-scale ICs [4].…”

Section: Introductionmentioning

confidence: 97%

Modeling of peak-to-peak switching noise along a vertical chain of power distribution TSV pairs in a 3D stack of ICs interconnected through TSVs

et al. 2010

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On-chip power supply noise has become a bottleneck in 3D ICs as scaling of the supply network impedance has not been kept up with increasing device densities and operating currents with each technology node due to limited wire resources. In this paper we proposed an efficient and accurate model to estimate peak-topeak switching noise, caused by simultaneous switching of logic loads along a vertical chain of power distribution TSV pairs in a 3D stack of ICs. The proposed model is quite accurate with only 2-3% difference from Ansoft Nexxim4.1 equivalent model. The proposed model is 3-4 times faster than Nexxim4.1 as well as consumes two times less memory as compared to Nexxim4.1equivalent model. We analyzed peak-to-peak switching noise along a vertical chain of power distribution TSV pairs by varying physical dimensions of TSVs and value of decoupling capacitance. We also thoroughly investigated the peak-to-peak noise sensitivity to TSV effective inductance and decoupling capacitance.

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Section: Introductionmentioning

confidence: 97%

Modeling of peak-to-peak switching noise along a vertical chain of power distribution TSV pairs in a 3D stack of ICs interconnected through TSVs

et al. 2010

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“…Existing work mainly came from two research communities, i.e., electronic design automation (EDA) and computer architecture. In the context of EDA, a significant amount of research has been done in the areas of physical design (e.g., see [1,16,25]) and thermal analysis and management (e.g., see [13,23,54]). As pointed out in [5], architectural innovations will play an at least equally important role as EDA innovations in order to fully exploit the potential of 3D integration.…”

Section: Introductionmentioning

confidence: 99%

DSP Systems using Three-Dimensional (3D) Integration Technology

Zhang¹,

Pan²,

Li³

2010

Handbook of Signal Processing Systems

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As three-dimensional (3D) integration technology is quickly maturing and steadily entering mainstream markets, it has begun to attract exploding interest from integrated circuit and system designers. This chapter discusses and demonstrates the exciting opportunities and potentials for digital signal processing (DSP) circuit and system designers to exploit 3D integration technology. In particular, this chapter advocates a 3D logic-DRAM integration paradigm and addresses the use of 3D logic-memory integration in both programmable digital signal processors and application-specific digital signal processing circuits. To further demonstrate the potential, this chapter presents case studies on applying 3D logic-DRAM integration to clustered VLIW (very long instruction word) digital signal processors and application-specific video encoders. Since DSP systems using 3D integration technology is still in its research infancy, by presenting some first discussions and results, the aim of this chapter is to motivate greater future efforts from DSP system research community to explore this new and rewarding research area.

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“…Sophisticated thermal management techniques have been developed to address potential problems [30]. Common techniques include (i) thermal-aware block placement to spread high-power blocks and (ii) insertion of thermal TSVs (or recently microfluidic channels) in order to increase the vertical (or horizontal) thermal conductivity of a 3D IC.…”

Section: B Thermal Managementmentioning

confidence: 99%

Multiobjective optimization of deadspace, a critical resource for 3D-IC integration

Knechtel

Markov

Lienig

et al. 2012

Proceedings of the International Conference on Computer-Aided Design

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Abstract-In 3D-IC integration and its implied resource optimization, a particularly critical resource is deadspace -regions between floorplan blocks. Deadspace is required for through-silicon via (TSV) planning and other related design tasks, but the effective use of this limited and highlycontested resource requires effort. While most previous work focuses on a single design issue at a time, we propose a lightweight multiobjective deadspace-optimization methodology that simultaneously optimizes interconnect, IR-drop, clock-tree size and maximal temperature. This methodology repeatedly re-evaluates design quality during early chip planning and uses resulting information to guide further optimization. Experimental results indicate that constructing an appropriate deadspace distribution improves design tradeoffs and is effective in practice.

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Addressing thermal and power delivery bottlenecks in 3D circuits

Cited by 32 publications

References 23 publications

Modeling of peak-to-peak switching noise along a vertical chain of power distribution TSV pairs in a 3D stack of ICs interconnected through TSVs

Modeling of peak-to-peak switching noise along a vertical chain of power distribution TSV pairs in a 3D stack of ICs interconnected through TSVs

DSP Systems using Three-Dimensional (3D) Integration Technology

Multiobjective optimization of deadspace, a critical resource for 3D-IC integration

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