Advanced Analysis of WLCSP Copper Interconnect Reliability under Board Level Drop Test

Tee, Tong Yan; BinTan, Long; Anderson, R.; Ng, Hun Shen; Low, Jim Hee; Khoo, Choong Peng; Moody, Robert; Rogers, Boyd

doi:10.1109/eptc.2008.4763574

Cited by 32 publications

(10 citation statements)

References 9 publications

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“…However, solder joint failure may not be applicable for certain WLCSP designs, which fail at board trace interconnect, die-side Cu RDL or CuiUBM interface during drop test. These types of failures were all reported in a recent publication by the authors [13]. This paper will focus on detailed analysis of copper board trace crack under drop test with board design guidelines recommended, so that true board level drop performance of WLCSP can be characterized.…”

Section: Introductionmentioning

confidence: 86%

Design for board trace reliability of WLCSP under drop test

Tee

Syed

et al. 2009

EuroSimE 2009 - 10th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelect

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Through an aggressive product development program which includes experiment and simulation, Amkor has developed the next level of WLCSP (CSpn1TM), a product which exhibits superior board level reliability when subjected to drop impact, a strong requirement for portable electronics. Failure mechanism of WLCSP under drop test has been established. Depending on type of WLCSP and test board design, 3 primary failure modes can be observed, i.e. copper (Cu) board trace crack, Cu RDL (Redistribution Layer) vertical crack and CulUBM (Under Bump Metallization) delamination. CSpnl can exhibit distinct failure modes under different test board and/or CSpnl designs, resulting in a vast difference in drop test lifetimes. The primary failure mode is shifted whenever the weakest link is removed through design improvement. This paper will focus on detailed analysis of copper board trace crack under drop test, using an integrated approach of testing, failure analysis, material characterization and modeling. Board design guidelines are formulated to understand the effects of 1/0 position, board trace routing direction, board trace width, tear drop design, PCB pad size, stack-up thickness, and alloy materials on board trace reliability. Comparison is also made on possible impact on Cu RDL reliability.

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Section: Introductionmentioning

confidence: 86%

Design for board trace reliability of WLCSP under drop test

Tee

Syed

et al. 2009

EuroSimE 2009 - 10th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelect

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“…In previous papers, a comparison between condition B and condition H has been made for Amkor's CSP"' stack-up [4][5][6]. The acceleration factor derived between condition H and condition B is approximately 1.8x [6,7].…”

Section: Ubm Characterizationmentioning

confidence: 99%

Advances in WLCSP Technologies to Enable Cost Reduction

Chilukuri¹,

Anderson²,

Rogers³

et al. 2010

Journal of Microelectronics and Electronic Packaging

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“…These stresses are often cyclic and result in failure due to fatigue in terms of trace crack. Researchers [Tee 2008] have shown that improvements in solder interconnect design has led to a shift in mode of failure from interconnect fracture to PCB copper trace cracks. Previously, the effect of trace orientation [Tee 2009] and fatigue behavior of copper traces in cyclic mechanical loading has been studied [Farley 2009].…”

Section: Introductionmentioning

confidence: 99%

Board trace fatigue models and design guidelines for electronics under shock-impact

Lall

Angral

Suhling

2010

2010 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems

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Driven by the trends towards miniaturization and increased functionality, modern electronic systems are being built into more intricate and smaller packages.The mechanical robustness of these smaller and more complex packages is of great concern to the electronics industry. With advances in packaging technology, more reliable interconnects are being designed as a result of which the accountability for failure shifts to copper traces which form the primary failure mode. Previous researchers have addressed copper trace fatigue reliability [Farley 2009] and existence of copper-trace failures in drop-shock [Tee 2009]. This paper addresses the need for life prediction models for PWB copper traces in shock and vibration environments. The study focuses on high cycle fatigue of copper traces which is simulated by subjecting the PWB to vibrations in first mode until failure. Owing to the complexity of the test vehicle, global-local finite element models were developed for simulating the board response. The study addresses the need for empirical rules for trace layout on the PWB which ensure maximum reliability. The effect of trace orientation, trace-pad fillet angle and trace width on its reliability has been investigated. Using Digital Image Correlation based strain responses and Finite Element Model based stress responses, mathematical models for damage accumulation and life prediction of copper traces have been formulated and validated with experimental failure statistics.

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Advanced Analysis of WLCSP Copper Interconnect Reliability under Board Level Drop Test

Cited by 32 publications

References 9 publications

Design for board trace reliability of WLCSP under drop test

Design for board trace reliability of WLCSP under drop test

Advances in WLCSP Technologies to Enable Cost Reduction

Board trace fatigue models and design guidelines for electronics under shock-impact

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