Design for board trace reliability of WLCSP under drop test

Tee, Tong Yan; Ng, Hun Shen; Syed, Ahmer; Anderson, R.; Khoo, Choong Peng; Rogers, Boyd

doi:10.1109/esime.2009.4938518

Cited by 18 publications

(9 citation statements)

References 13 publications

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“…Cu 6 Sn 5 or (Ni, Cu) 3 Sn 4 intermetallic compounds during RoHS conform soldering. Recently, several researchers published a switching of the dominating failure mode to PCB pad lifts and broken copper traces [5][6][7].…”

Section: Failure Analysesmentioning

confidence: 99%

A detailed investigation of the failure formation of copper trace cracks during drop tests

Kraemer

Wiese

Rzepka

et al. 2010

3rd Electronics System Integration Technology Conference ESTC

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The development cycle of new products can be dramatically reduced if exact lifetime models are at hand. This requires the precise knowledge of the failure modes and the failure position under all test and service conditions. In case of dynamic mechanical loads like drops of BGA modules, broken copper traces at the PCB side are more and more often observed to be the ultimate failure effect. However, straightforward FEM simulations have shown unrealistic high stress and strain results not matching experimental observations which prove that a realistic representation of this failure is not trivial. A comprehensive physical investigation of the failure formation combined dye and pry tests, electron backscatter diffraction EBSD and 3-D X-ray tomography analyses. The results revealed the complex nature of the dynamic failure propagation. In addition to the ultimate fracture of the copper trace cracking of the IMC on top of the PCB pad was detected. Both failure modes are initiated during the drop event at different times and propagate with different speeds. Both failures are mutually interacting with each other with no single mode alone dominating the failure evolution. Hence, lifetime modeling needs to account for both failure modes in order to capture the copper trace stress realistically. Numerical simulations have been conducted investigating the experimental findings. A small flaw already reduces the stress level at the pad/solder interface substantially. The IMC crack is found to be initiated first reaching a stable length at the half pad diameter. In this condition, the copper trace is stressed at a lower level accumulating plastic strain enough to ultimately create the trace fracture in a realistic number of cycles. A very realistic 2nd level interconnection model has been created based on the combined failure mechanism found by comprehensive physical failure analysis, and the numerical simulations. It now allows lifetime prediction of BGA assemblies under drop test conditions with high accuracy and reliably. Hence, it will be able to replace expensive experiments by fast numerical assessments in the design optimization phase of product and technology development

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Section: Failure Analysesmentioning

confidence: 99%

A detailed investigation of the failure formation of copper trace cracks during drop tests

Kraemer

Wiese

Rzepka

et al. 2010

3rd Electronics System Integration Technology Conference ESTC

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show abstract

“…Researchers [Tee 2008] have shown that improvements in solder interconnect design has led to a shift in mode of failure from interconnect fracture to PCB copper trace cracks. Previously, the effect of trace orientation [Tee 2009] and fatigue behavior of copper traces in cyclic mechanical loading has been studied [Farley 2009]. …”

Section: Introductionmentioning

confidence: 99%

“…With advances in packaging technology, more reliable interconnects are being designed as a result of which the accountability for failure shifts to copper traces which form the primary failure mode. Previous researchers have addressed copper trace fatigue reliability [Farley 2009] and existence of copper-trace failures in drop-shock [Tee 2009]. This paper addresses the need for life prediction models for PWB copper traces in shock and vibration environments.…”

mentioning

confidence: 98%

Board trace fatigue models and design guidelines for electronics under shock-impact

Lall

Angral

Suhling

2010

2010 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems

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Driven by the trends towards miniaturization and increased functionality, modern electronic systems are being built into more intricate and smaller packages.The mechanical robustness of these smaller and more complex packages is of great concern to the electronics industry. With advances in packaging technology, more reliable interconnects are being designed as a result of which the accountability for failure shifts to copper traces which form the primary failure mode. Previous researchers have addressed copper trace fatigue reliability [Farley 2009] and existence of copper-trace failures in drop-shock [Tee 2009]. This paper addresses the need for life prediction models for PWB copper traces in shock and vibration environments. The study focuses on high cycle fatigue of copper traces which is simulated by subjecting the PWB to vibrations in first mode until failure. Owing to the complexity of the test vehicle, global-local finite element models were developed for simulating the board response. The study addresses the need for empirical rules for trace layout on the PWB which ensure maximum reliability. The effect of trace orientation, trace-pad fillet angle and trace width on its reliability has been investigated. Using Digital Image Correlation based strain responses and Finite Element Model based stress responses, mathematical models for damage accumulation and life prediction of copper traces have been formulated and validated with experimental failure statistics.

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“…Three primary failure modes are often observed in drop test for BGA and WLP packages: copper trace crack or pad crater in printed circuit board (PCB), crack at intermetallic (IMC) layer of solder joints, and die-level cracks, such as in RDL or copper interconnect. Because PCB failures (trace crack or pad crater) provide a misrepresentation of the actual package performance, some board design guidelines have been further recommended and adopted to avoid such failure modes during test [5].…”

mentioning

confidence: 99%

“…The accuracy of the local modeling (or sub-modeling) technique has been verified by the comparison of board strain calculations from both global and local models [17]. Numerous experimental and test data have been reported for solder joint reliability under impact loading on BGA packages and WLPs [5], [13], [23]. However, little study has been conducted across an array of various package structures for solder joint reliability under impact loading.…”

mentioning

confidence: 99%

Effects of Package Level Structure and Material Properties on Solder Joint Reliability Under Impact Loading

Fan

Ranouta

Dhiman

2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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In this paper, the effects of package level structures and material properties on solder joint reliability subjected to impact loading are investigated by the integrated experimental testing, failure analysis, and finite element modeling. Three different package structures: ball on I/O wafer level package (WLP), copper post WLP, and chip-scale (CS) ball grid array (BGA) package, are studied. Experimental testing based on JESD22-B111 is conducted to obtain the components' failure mode, rate, location, and the corresponding board strains and accelerations. Finite element models are developed and validated against the experimental results. For a CS BGA package, the compliance of the plastic substrate/mold compound provides a "stress buffer mechanism" at corner joints in BGA to relieve stresses. For a copper post (or pillar) WLP, wafer level epoxy, which encapsulates copper pillars, serves as a compliant layer for solder joint stress reduction under dynamic loading. Comprehensive data from simulation and experimental results show that package structure and material properties play a significant role on the dynamic responses of solder joints. The actual solder joint reliability performance of a CS BGA or WLP package depends on the resultant effects of package structure, material properties, package body size, and the component locations. Index Terms-Ball grid array (BGA), compliant layer, dynamics, finite element analysis (FEA), impact loading, JESD22-B111, reliability, solder joints, wafer level package (WLP).

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Design for board trace reliability of WLCSP under drop test

Cited by 18 publications

References 13 publications

A detailed investigation of the failure formation of copper trace cracks during drop tests

A detailed investigation of the failure formation of copper trace cracks during drop tests

Board trace fatigue models and design guidelines for electronics under shock-impact

Effects of Package Level Structure and Material Properties on Solder Joint Reliability Under Impact Loading

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