Advanced automatic test pattern generation techniques for path delay faults

Schulz, Michael; Fuchs, Karl Josef; Fink, F.

doi:10.1109/ftcs.1989.105541

Cited by 84 publications

(19 citation statements)

References 10 publications

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“…Most of them are based on either branch-and-bound algorithms [Fuchs 47:2 A. Mondal et al et al 1993Mondal et al et al , 1994Schulz et al 1989] or Boolean satisfiability [Bhattacharya et al 1995;McGeer et al 1991]. This article proposes the following contributions.…”

Section: Introductionmentioning

confidence: 95%

Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults

Mondal

Chakrabarti

Dasgupta

2012

ACM Trans. Des. Autom. Electron. Syst.

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We present a symbolic-event-propagation-based scheme to generate hazard-free tests for robust path delay faults. This approach identifies all robustly testable paths in a circuit and the corresponding complete set of test vectors. We address the problem of finding a minimal set of test vectors that covers all robustly testable paths. We propose greedy and simulated-annealing-based algorithms to find the same. Results on ISCAS89 benchmark circuits show a considerable reduction in test vectors for covering all robustly testable paths.

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Section: Introductionmentioning

confidence: 95%

Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults

Mondal

Chakrabarti

Dasgupta

2012

ACM Trans. Des. Autom. Electron. Syst.

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“…This is important because the number of path delay faults in modern designs quickly become too many to enumerate, even when restricting to critical paths (see [4,7]). The increased complexity of modern designs indicates a need for implicit fault coverage tools that can work with large test sets and large designs.…”

Section: Introductionmentioning

confidence: 99%

A novel parallel adaptation of an implicit path delay grading method

Lenox

Tragoudas

2014

Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI

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For large modern circuits, it is desirable to trade hardware cost for time when making path delay fault coverage estimates, especially as a subroutine for ATPG and timing analysis solutions. A parallel adaptation of an established framework for implicit path delay fault grading on with a GPGPU implementation is presented. Experimental evaluation on a NVIDIA Tesla C2075 GPU shows on average 50x speedup against the basic version for the framework on an Intel Xeon E5504 host system. Over a 1200x speedup is observed against a single-threaded, more complex version in the framework which grades more faults.

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“…Two issues need to be addressed when considering path delay faults: 1) the number of paths in a circuit can be very high; in the worst case, it can be exponential in the number of lines in the circuit; and 2) many of the path delay faults are undetectable. Path selection procedures [2]- [12] address the first issue by selecting a subset of path delay faults to be considered during test generation. One approach to path selection is to consider only the longest (critical) paths in the circuit [2].…”

Section: Introductionmentioning

confidence: 99%

“…Path selection procedures [2]- [12] address the first issue by selecting a subset of path delay faults to be considered during test generation. One approach to path selection is to consider only the longest (critical) paths in the circuit [2]. Procedures that improve the accuracy of critical path identification by performing timing analysis were described in [4]- [6], [8], [9], and [11].…”

Section: Introductionmentioning

confidence: 99%

A Metric for Identifying Detectable Path Delay Faults

Pomeranz

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Path delay faults are used for modeling small delay defects. Due to the large numbers of paths and the large numbers of undetectable path delay faults, test generation procedures for path delay faults use path selection procedures and procedures for the identification of undetectable faults to facilitate test generation. To complement these procedures, this paper describes a metric for assessing the likelihood that a path delay fault is detectable. Path selection procedures should prefer such faults in order to yield sets of target faults that are detectable even if not all the undetectable faults are identified prior to test generation. The metric is defined such that it allows all the path delay faults with the same value of the metric (the same likelihood of being detectable) to be enumerated together. The metric is computed based on the numbers of detections of transition faults under a test set for such faults, and requires N-detection fault simulation of transition faults for a sufficiently large value of N. The results of test generation for path delay faults confirm that faults with higher values of the metric are more likely to be detectable.

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Advanced automatic test pattern generation techniques for path delay faults

Cited by 84 publications

References 10 publications

Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults

Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults

A novel parallel adaptation of an implicit path delay grading method

A Metric for Identifying Detectable Path Delay Faults

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