Advanced Bit Flip Concatenates BCH Code Demonstrates 0.93% Correctable BER and Faster Decoding on (36 864, 32 768) Emerging Memories

Ning, Sheyang

doi:10.1109/tcsi.2018.2840350

Cited by 12 publications

(1 citation statement)

References 21 publications

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“…The execution time and BER performance are better in software-based than hardware approaches. However, BCH codes using applicationspecific integrated circuits (ASICs) or Field programmable gate arrays (FPGAs) as hardware approaches provide high Throughput, low-latency, and low-complexity features than software-based approaches [7]- [10].…”

Section: Introductionmentioning

confidence: 99%

An efficient high throughput BCH module for multi-bits error correction mechanism on hardware platform

Puttaraju,

Muniyappa

2024

IJEECS

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The bose-chaudhuri-hocquenghem (BCH) codes are a cyclic error correction codes (ECC) class. The BCH is constructed by using a polynomial over the Galois field. The BCH codes can detect and correct the multi-bits with an easy decoding mechanism. The BCH codes are used in most of the storage device's cryptography, disk drives, and satellite applications. This manuscript presents an efficient high-throughput BCH module with an encoding and decoding mechanism for multi-bit corrections. The BCH code of (15, k) is used to construct the encoder and decoder architectures. The BCH encoder decoder (ED) module with single error correction (SEC), double error correction (DEC), and triple-error correction (TEC) are discussed in detail. The BCH encoder module uses a linear feedback shift register (LFSR). The BCH decoder with SEC and DEC is constructed using the syndrome generator module (SGM) and chien search module (CSM). The BCH decoder with TEC is designed using SGM, inversion-based berlekamp-massey-algorithm (BMA), and CSMs. The BCH-ED module with SEC, DEC, and TEC utilizes <1 % chip area on Artix-7 FPGA. The BCH-ED with SEC, DEC, and TEC achieves a throughput of 7.13 Gbps, 1.2 Gbps, and 0.803 Gbps, respectively. Lastly, the BCH module is compared with existing BCH approaches with better improvement in chip area, frequency, and throughput parameters.

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Section: Introductionmentioning

confidence: 99%