Novel write verification methods are proposed to improve write speed, energy and endurance of resistive random access memory (ReRAM). Flexible write stress is implemented during reset w/ verification and set w/ verification, by which the pulse width or voltage can be decremented as well as incremented. Proposed reset w/ verification and set w/ verification methods are characterized by measuring 50nm Al x O y ReRAM devices and compared against conventional methods. Improvements of 1.9× average endurance increase, or 1.4× average endurance increase with 17% write time, the reset time plus set time decrease and 17% average write energy reduction are demonstrated.Index Terms-ReRAM, write with verification, ReRAM endurance, ReRAM write speed, ReRAM write energy. I. INTRODUCTIONResistive random access memory (ReRAM) is considered one of the most promising next generation nonvolatile memories due to its potential to provide fast write time, endurance and scalability [1]. However, ReRAM still faces several problems before commercialization. One of the issues is write performance degradation, in which switching to HRS or LRS becomes increasingly difficult over the lifetime of the device [2, 3]. In a prior work [3], HfO 2 ReRAM device endurance was enhanced by introducing write with verification and increasing write stress adaptively as the device cycles. Further, increasing the voltage during set and increasing the pulse width (PW) during reset was found to be the most effective method to improve endurance. In this paper, a matrix of the previously proposed three reset cycling methods to determine reset pulse width (W1, W2 and W3) and three set cycling methods to determine set voltage (V1, V2 and V3) are applied to 50nm Al x O y ReRAM devices. Further, a new reset cycling method is proposed in which, the initial reset pulse width T ini_reset has the option to be decremented as well as incremented, and successive reset pulses during reset w/ verification are incremented by accelerated, rather than the conventional linear steps. The second proposal for set cycling applies the similar concepts of the decrement option to the voltage of the initial set pulse V ini_set . Compared with the conventional methods, applying the proposed reset and proposed set methods can increase the device average endurance by 1.9 times. Using proposed reset method with conventional set method V2, 1.4× endurance enhancement with 17% write time, the reset plus set write time reduction and 17% write energy saving can be achieved.

In order to decrease program bit error rate (BER) of array-level operation in Al x O y resistive random access memory (ReRAM), program BERs are compared by using 4 × 4 basic set and reset with verify methods on multiple 1024-bit-pages in 50 nm, mega-bit class ReRAM arrays. Further, by using an optimized reset method, 8.5% total BER reduction is obtained after 104 write cycles due to avoiding under-reset or weak reset and ameliorating over-reset caused wear-out. Then, under-set and over-set are analyzed by tuning the set word line voltage (VWL) of ±0.1 V. Moderate set current shows the best total BER. Finally, 2000 write cycles are applied at 125 and 25 °C, respectively. Reset BER increases 28.5% at 125 °C whereas set BER has little difference, by using the optimized reset method. By applying write cycles over a 25 to 125 to 25 °C temperature variation, immediate reset BER change can be found after the temperature transition.

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