Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units

Preiss, J.; Boersma, Maarten; Mueller, Silvia Melitta

doi:10.1109/arith.2009.17

Cited by 15 publications

(8 citation statements)

References 8 publications

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“…From a power-consumption perspective, choosing to run in single-precision mode, in lieu of double precision, is potentially beneficial in three ways: a. Since single-precision instructions do not use all the FPU hardware required for double-precision instructions, 13 this means that, theoretically, they require less active power to execute and, thus, reduce overall power consumption, as compared to double-precision operations. b.…”

Section: Application-initiated Techniquesmentioning

confidence: 99%

Power versus performance tradeoffs of GPU-accelerated backprojection-based synthetic aperture radar image formation

Portillo

Arunagiri

Teller

et al. 2011

Modeling and Simulation for Defense Systems and Applications VI

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The continuing miniaturization and parallelization of computer hardware has facilitated the development of mobile and field-deployable systems that can accommodate terascale processing within once prohibitively small size and weight constraints. General-purpose Graphics Processing Units (GPUs) are prominent examples of such terascale devices. Unfortunately, the added computational capability of these devices often comes at the cost of larger demands on power, an already strained resource in these systems. This study explores power versus performance issues for a workload that can take advantage of GPU capability and is targeted to run in field-deployable environments, i.e., Synthetic Aperture Radar (SAR). Specifically, we focus on the Image Formation (IF) computational phase of SAR, often the most compute intensive, and evaluate two different state-of-the-art GPU implementations of this IF method. Using real and simulated data sets, we evaluate performance tradeoffs for single-and double-precision versions of these implementations in terms of time-to-solution, image output quality, and total energy consumption. We employ fine-grain direct-measurement techniques to capture isolated power utilization and energy consumption of the GPU device, and use general and radarspecific metrics to evaluate image output quality. We show that double-precision IF can provide slight image improvement to low-reflective areas of SAR images, but note that the added quality may not be worth the higher power and energy costs associated with higher precision operations.

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Section: Application-initiated Techniquesmentioning

confidence: 99%

Power versus performance tradeoffs of GPU-accelerated backprojection-based synthetic aperture radar image formation

Portillo

Arunagiri

Teller

et al. 2011

Modeling and Simulation for Defense Systems and Applications VI

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“…In the context of instruction-dependent techniques, there is interesting research done in the past for scalar processors [8]. The main advantages of our ImplCG proposal over the mentioned research are: (1) we apply the technique for a variable number of pipeline stages, (2) we evaluate power, timing, and area, and (3) we propose the technique for vector processors.…”

Section: Implicit Scalar Operand Clock-gating (Implcg)mentioning

confidence: 99%

“…Clock-gating is a common method to reduce switching power in synchronous pipelines [6,7,8,9,10]. It is practically a standard in low-power design.…”

Section: Introductionmentioning

confidence: 99%

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Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add

Ratkovic¹,

Palomar

Stanić

et al. 2018

IEEE Trans. VLSI Syst.

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The need for power-efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a re-tailoring for the mobile market that they are entering now. Floating point fused multiply-add, being a functional unit with high power consumption, deserves special attention. Although clock-gating is a well-known method to reduce switching power in synchronous designs, there are unexplored opportunities for its application to vector processors, especially when considering active operating mode. In this research, we comprehensively identify, propose, and evaluate the most suitable clock-gating techniques for vector fused multiply-add units (VFU). These techniques ensure power savings without jeopardizing the timing. We evaluate the proposed techniques using both synthetic and "real world" application-based benchmarking. Using vector masking and vector multi-lane-aware clock-gating, we report power reductions of up to 52%, assuming active VFU operating at the peak performance. Among other findings, we observe that vector instruction-based clock-gating techniques achieve power savings for all vector floating-point instructions. Finally, when evaluating all techniques together, using "real world" benchmarking, the power reductions are up to 80%. Additionally, in accordance with processor design trends, we perform this research in a fully parameterizable and automated fashion.

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“…Amaricai, Alexandru, MirceaVladutiuet al [20] proposed combined operation of floating-point (FP) division followed by addition/subtraction-the divide-add fused (DAF). The main aim of this proposed method is to enhance the precision and performance of application where this combine designed is implementing.…”

Section: Introductionmentioning

confidence: 99%

Implementation of Fast and Efficient Mac Unit on FPGA

Raghav¹,

Mittal²

2016

IJMSC

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Floating-point arithmetic operations on digital systems have become an important aspect of research in recent times. Many architecture have been proposed and implemented by various researchers and their merits and demerits are compared. Floating point numbers are first converted into the IEEE 754 single or double precision format in order to be used in the digital systems. The arithmetic operations require various steps to be followed for the correct and accurate steps. In the proposed approach a fast and area efficient Carry Select Adder are implemented along with the parallel processing of various units used in the architecture. The result also verifies the proposed approach that shows a decrement of 27 % in the combinational path delay with an increment of around 8% in the number of LUTs used.

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Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units

Cited by 15 publications

References 8 publications

Power versus performance tradeoffs of GPU-accelerated backprojection-based synthetic aperture radar image formation

Power versus performance tradeoffs of GPU-accelerated backprojection-based synthetic aperture radar image formation

Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add

Implementation of Fast and Efficient Mac Unit on FPGA

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