Advanced Components in the Variable Precision Floating-Point Library

Wang, Xiaojun; Braganza, S.; Leeser, Miriam

doi:10.1109/fccm.2006.21

Cited by 43 publications

(27 citation statements)

References 12 publications

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“…It is parameterizable, highly parallel, and fully pipelined on a larger and faster Xilinx Virtex2 XC2V6000 FPGA. The novel part of this implementations of K-means clustering is the use of floating-point divide [18]. Other than the most popular digit recurrence division algorithms [16,17,19], we use the Taylor series based algorithm [7] that only needs a mix of small lookup tables and small multipliers.…”

Section: Related Workmentioning

confidence: 99%

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K-means Clustering for Multispectral Images Using Floating-Point Divide

Meulenaer

Gosset

Dormale

et al. 2007

15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007)

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Many signal processing algorithms can be accelerated using reconfigurable hardware. To achieve a good speedup compared to running software on a general purpose processor, fine-grained control over the bitwidth of each component in the datapath is desired. This goal can be achieved by using NU's variable precision floating-point library. To analyze the usefulness of the floating-point divide unit, we incorporate it into our previous implementation of the Kmeans clustering algorithm applied to multispectral satellite images. With the lack of a floating-point divide hardware implementation, the mean updating step in each iteration of the K-means algorithm had to be moved to the host computer for calculation. The new means calculated on the host then had to be moved back to the FPGA board for the next iteration of the algorithm. This added data transfer overhead between the host and the FPGA board. In this work, we use the new fp div module to implement the mean updating step in FPGA hardware. This greatly reduces the communication overhead between host and FPGA board and further accelerates run time. The Kmeans clustering example illustrates the use of the fp div, fix2float and float2fix modules seamlessly assembled together in a real application. It is the first implementation that has the complete K-means computation done in FPGA hardware. Our results show that the hardware implementation achieves a speedup of over 2150x for core computation time and about 11x for total run time including data transfer time. They also show that the divide in FPGA hardware is 100 times faster than in software. Moreover, implementing divide in the FPGA frees the host to work on other tasks concurrently with K-means clustering, thus providing further speedup by allowing the image analyst to exploit this coarse grained parallelism.

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Section: Related Workmentioning

confidence: 99%

“…We have previously presented a floating-point divide module [18] as part of the NU floating-point library. Our floating-point divide is fully pipelined, non-iterative, and has low latency.…”

Section: Introductionmentioning

confidence: 99%

K-means Clustering for Multispectral Images Using Floating-Point Divide

Meulenaer

Gosset

Dormale

et al. 2007

15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007)

Self Cite

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“…However, with their ever-increasing computing power, FPGAs are now useful for a much broader range of applications, including those requiring floating-point arithmetic. Floating-point units with various precisions have been designed [25], [26]. FPGA-based architectures have also been proposed for computationally intensive applications [27].…”

Section: Field-programmable Gate Arraysmentioning

confidence: 99%

High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware

Zhuo

Prasanna

2008

IEEE Trans. Comput.

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Abstract-Numerical linear algebra operations are key primitives in scientific computing. Performance optimizations of such operations have been extensively investigated. With the rapid advances in technology, hardware acceleration of linear algebra applications using field-programmable gate arrays (FPGAs) has become feasible. In this paper, we propose FPGA-based designs for several basic linear algebra operations, including dot product, matrix-vector multiplication, matrix multiplication, and matrix factorization. By identifying the parameters for each operation, we analyze the trade-offs and propose a high-performance design. In the implementations of the designs, the values of the parameters are determined according to the hardware constraints, such as the available chip area, the size of available memory, the memory bandwidth, and the number of I/O pins. The proposed designs are implemented on Xilinx Virtex-II Pro FPGAs. Experimental results show that our designs scale with the available hardware resources. Also, the performance of our designs compares favorably with that of general-purpose processor-based designs. We also show that, with faster floating-point units and larger devices, the performance of our designs increases accordingly.

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“…Different approaches have been proposed for the calculation of division operation in hardware: Logarithmic Number System (LNS) based implementations [1], variable precision division [2], functional iteration algorithms [3], CORDIC implementations [4] or combinations of table lookup with Taylor series expansions [5] are illustrative examples. In [6], a comprehensive survey on division algorithms is presented, which classifies the algorithms based upon their hardware implementations and impact on system design.…”

mentioning

confidence: 99%

Iterative-Gradient Based Complex Divider FPGA Core with Dynamic Configurability of Accuracy and Throughput

López‐Martínez

Castillo-Sánchez

Entrambasaguas

et al. 2010

J Sign Process Syst

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A field programmable gate array (FPGA) implementation of a highly configurable complex divider is presented, based on an iterative gradient algorithm. The proposed architecture allows to configure both the accuracy and the throughput of the division operation, which makes it suitable for diverse applications with different requirements. Results show how various throughputs can be achieved under different maximum error and iteration limit configurations. Besides, the resource occupation is considerably small, compared with previous solutions.

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Advanced Components in the Variable Precision Floating-Point Library

Cited by 43 publications

References 12 publications

K-means Clustering for Multispectral Images Using Floating-Point Divide

K-means Clustering for Multispectral Images Using Floating-Point Divide

High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware

Iterative-Gradient Based Complex Divider FPGA Core with Dynamic Configurability of Accuracy and Throughput

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