Advanced Computer Architecture and Parallel Processing

El‐Rewini, Hesham; Abd-El-Barr, Mostafa

doi:10.1002/0471478385

Cited by 97 publications

(98 citation statements)

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“…It is worth mentioning that structuring this computationally intensive application has been obtained by methodological targeting to emerging (hierarchical) multiprocessing platforms. Accordingly, a distinctive feature of the proposed dual-level parallel model resides in its ability to achieve good performance in exploiting the available degrees of parallelism of the current HPC platforms [4]; this includes both shared-memory and distributed-memory architectures. Furthermore, we have experimentally demonstrated the validity of our approach.…”

Section: Discussionmentioning

confidence: 99%

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A Parallel Computational Model for Multichannel Phase Unwrapping Problem

Imperatore¹,

Pepe²,

Lanari³

2015

Proceedings of Fringe 2015: Advances in the Science and Applications of SAR Interferometry and Sentinel-1 InSAR Workshop

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In this paper, a parallel model for the solution of the computationally intensive multichannel phase unwrapping (MCh-PhU) problem is proposed. Firstly, the Extended Minimum Cost Flow (EMCF) algorithm for solving MCh-PhU problem is revised within the rigorous mathematical framework of the discrete calculus; thus permitting to capture its topological structure in terms of meaningful discrete differential operators. Secondly, emphasis is placed on those methodological and practical aspects, which lead to a parallel reformulation of the EMCF algorithm. Thus, a novel dual-level parallel computational model, in which the parallelism is hierarchically implemented at two different (i.e., process and thread) levels, is presented. The validity of our approach has been demonstrated through a series of experiments that have revealed a significant speedup. Therefore, the attained highperformance prototype is suitable for the solution of large-scale phase unwrapping problems in reasonable time frames, with a significant impact on the systematic exploitation of the existing, and rapidly growing, large archives of SAR data.

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Section: Discussionmentioning

confidence: 99%

“…Recasting the original algorithm into a form (decomposition pattern) [4]- [6] that exposes available concurrency inherent into the problem has been our primary concern. Flexibility, simplicity and efficiency/scalability have been three main guidelines adopted for the decomposition pattern strategy.…”

Section: Parallel Formulation Of the Emcf Algorithmmentioning

confidence: 99%

A Parallel Computational Model for Multichannel Phase Unwrapping Problem

Imperatore¹,

Pepe²,

Lanari³

2015

Proceedings of Fringe 2015: Advances in the Science and Applications of SAR Interferometry and Sentinel-1 InSAR Workshop

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“…A shared memory is simple and easy to implement. However, it does require a good memory-to-processor interconnect and a consistency protocol to maintain memory coherence [110]. From a software perspective, the concept of shared memory provides for inter-process communications and makes available 3155 shared support such as shared libraries and program execution tools.…”

Section: Mimd Architecturesmentioning

confidence: 99%

High‐performance computing: to boldly go where no human has gone before

Limet

Smari

Spalazzi

2015

Concurrency and Computation

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International audienceComputing and computational science are well on their way to enter into the exascale era while High Performance Computing (HPC) is now present in many spheres and domains of modern society. New technologies such as cloud computing, big data, and connected objects open many perspectives and possibilities that were unattainable until now. These are high times for computing and for HPC in particular. The High Performance Computing \& Simulation conference aims to bring together researchers working on various aspects of HPC, their design and use, and their applications. As has been the conference tradition, selected extended papers of HPCS 2012 are presented in this special issue. These should be interesting contributions that supplement the current state-of-the-art research in HPC. To relate these works and highlight their value, in this article, we briefly trace back the history of HPC, sketch the state of the present research and development in the field, and project some of the challenges and future trends anticipated

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“…Moreover, the execution Reduction Ratio (RR) is computed against the sequential case. The calculation of PID-loop speed-up is based on the "Equal Duration Model" [18]. The speedup factor of a parallel system can be defined as the ratio between the time taken by a single processor to solve a given problem instance to the time taken by a parallel system consisting of (n) processors to solve the same problem instance.…”

Section: A Debugging the Parallel Algorithmmentioning

confidence: 99%

Quad-Core MPSoC Architecture for PID-Based Embedded Control Systems

Youness¹,

Khaled²,

Moness³

2013

IJCTE

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Abstract-Modern embedded control systems require new techniques to fulfill the rapid increase in control requirements and constraints. Multiprocessor systems have been proposed as a promising solution for modern digital control systems. Embedded control systems need to meet hard real-time deadlines, while conducting additional tasks like tuning of control parameters or executing a fault-tolerance algorithm. In this paper, a novel low-cost custom FPGA-based quad-core multiprocessor system-on-chip (MPSoC) architecture prototype is introduced to enhance the performance of legacy digital PID controllers. Due to its inherent parallelism, the PID controller can be mapped directly to the proposed architecture which is built-up using four soft-core microprocessors. The digital PID algorithm is restructured to fit to the introduced system. The main contribution of this paper is a throughput-oriented high-performance low-cost digital PID controller. Results showed remarkable reductions in the execution time of the control loop of the introduced parallel PID controller.

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Advanced Computer Architecture and Parallel Processing

Cited by 97 publications

References 0 publications

A Parallel Computational Model for Multichannel Phase Unwrapping Problem

A Parallel Computational Model for Multichannel Phase Unwrapping Problem

High‐performance computing: to boldly go where no human has gone before

Quad-Core MPSoC Architecture for PID-Based Embedded Control Systems

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