Advanced flip chip encapsulation: transfer molding process for simultaneous underfilling and postencapsulation

Becker, K.-F.; Braun, T.; Koch, M.; Ansorge, F.; Aschenbrenner, R.; Reichl, H.

doi:10.1109/polytr.2001.973270

Cited by 8 publications

(2 citation statements)

References 4 publications

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“…On the previous literature about flip chip molding process itself [10], the mold tool should be optimized by geometrical means that is creating similar flow resistance over and under the flip chip. It is difficult to control the process and the package design.…”

Section: Muf Process and Doe By Sip Module Layout Designmentioning

confidence: 99%

MUF Technology Development for SiP Module

Kweon

Kim

et al. 2011

ECS Trans.

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In this study, we developed the molded underfill (MUF) technology for system in package (SiP) module with fine pitch flip chip in RF application, in which two flip chips, LC filter, and additional passive components are integrated sideby-side. This study covered not only MUF reliability performance but also MUF design study focused on minimizing voids between flip chip bumps in the SiP module. The investigation comprises several aspects: A design study that present a printed circuit board (PCB) and epoxy molding compound (EMC) selection approach, air vent design of cavity vacuum molding, and results of void free from Design of Experiment (DOE) of several SiP module layouts. In the end, Scanning Acoustic Tomography (SAT) result of void, moisture sensitivity test, thermal cycle test and pressure cooker test had also been carried out for reliability evaluation. The test result shows that the optimized SiP module with fine flip pitch has a good reliability performance.

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Section: Muf Process and Doe By Sip Module Layout Designmentioning

confidence: 99%

MUF Technology Development for SiP Module

Kweon

Kim

et al. 2011

ECS Trans.

View full text Add to dashboard Cite

show abstract

“…In fact, voids have been observed in the molded underfill packages using an acoustic microscope [53]. Several molding processes can be used to minimize this geometry effect [54]. One way is to use mold vents as shown in Fig.…”

Section: Molded Underfillmentioning

confidence: 99%

Recent Advances in Flip-Chip Underfill: Materials, Process, and Reliability

Zhang

Wong

2004

IEEE Trans. Adv. Packag.

200

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In order to enhance the reliability of a flip-chip on organic board package, underfill is usually used to redistribute the thermomechanical stress created by the coefficient of thermal expansion (CTE) mismatch between the silicon chip and organic substrate. However, the conventional underfill relies on the capillary flow of the underfill resin and has many disadvantages. In order to overcome these disadvantages, many variations have been invented to improve the flip-chip underfill process. This paper reviews the recent advances in the material design, process development, and reliability issues of flip-chip underfill, especially in no-flow underfill, molded underfill, and wafer-level underfill. The relationship between the materials, process, and reliability in these packages is discussed.

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Flip-Chip Underfill: Materials, Process and Reliability

Zhang

Wong

2009

Materials for Advanced Packaging

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Advanced flip chip encapsulation: transfer molding process for simultaneous underfilling and postencapsulation

Cited by 8 publications

References 4 publications

MUF Technology Development for SiP Module

MUF Technology Development for SiP Module

Recent Advances in Flip-Chip Underfill: Materials, Process, and Reliability

Flip-Chip Underfill: Materials, Process and Reliability

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