In recent years, an increasing number of mobile electronic products such as mobile communicators, combining the functions of a mobile phone and a PDA are beginning to emerge. These devices are highly miniaturized and yet provide a variety of functions at ever higher speeds. Additionally, the product cycle time is getting faster, requiring short design and production cycles at ever lower cost. These trends are posing great set of challenges for the microelectronics and packaging and assembly industry. There seem to be two approaches to solve these challenges-system-in-package (SIP) by stacking of packaged integrated circuits (ICs) or system-on-package (SOP) by stacking of packages with embedded active and passive components. The buried components in SOP require significantly less space in z direction, thereby allowing the formation of three-dimensional (3-D) stackable packages. In this paper, two approaches for stacking SOPs were presented, the so-called chip-in-polymer (CIP) technology and duromer molded interconnect device (MID)/WLP technology.Index Terms-Embedded passives, modular systems, molded interconnect device (MID), packaging, system-on-package (SOP).

One of the general trends in microelectronics packaging is the constant miniaturization of devices. This has led to the development of maximum miniaturization of components on Si level, i.e., CSPs and Flip Chips. To further integrate more functionality into devices, and to further increase the degree of miniaturization, packaging development focus is switching from single chip packaging to the realization of systems in package, SiPs. Two main approaches do exist to realize this goal: one is to integrate all components into one dedicated package, yielding maximum miniaturization for a special application, but little flexibility as far as system design is concerned. The other is to create modular stackable components that can be assembled into a functional system. This integrates both flexibility in system design by exchangeable components and increased reliability potential, as single components can be tested separately. This last approach was considered a promising choice for the generation of SiPs. Within this paper a packaging process is introduced that allows the wafer level manufacturing of stackable, encapsulated devices. Using a transfer molded epoxy demonstrator, a proof-of-concept is performed showing the feasibility of the stackable package approach. This is achieved by combining wafer level encapsulation and molded interconnect device technology. An electroless process for metallization and laser techniques for structuring the metallization layer have been applied to generate structures for reliable interconnects capable for the use of lead-free solders. Summarized, this paper presents the process development and feasibility analysis of wafer level packaging technologies for modular SiP solutions based on a duromer MID approach.

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