Even though electroless Ni-P and Sn-Ag-Cu solders are widely used materials in flip-chip bumping technologies, interfacial reactions of the ternary Cu-NiSn system are not well understood. The growth of intermetallic compounds (IMCs) at the under bump metallization (UBM)/solder interface can affect solder-joint reliability, so analysis of IMC phases and understanding their growth kinetics are important. In this study, interfacial reactions between electroless Ni-P UBM and the 95.5Sn-4.0Ag-0.5Cu alloy were investigated, focusing on identification of IMC phases and IMC growth kinetics at various reflowing and aging temperatures and times. The stable ternary IMC initially formed at the interface after reflowing was the (Cu,Ni) 6 Sn 5 phase. However, during aging, the (Cu,Ni) 6 Sn 5 phase slowly changed into the quaternary IMC composed of Cu, Ni, Sn, and a small amount of Au. The Au atoms in the quaternary IMC originated from immersion Au plated on electroless Ni-P UBM. During further reflowing or aging, the (Ni,Cu) 3 Sn 4 IMC started forming because of the limited Cu content in the solder. Morphology, composition, and crystal structure of each IMC were identified using transmission electron microscopy (TEM) and scanning electron microscopy (SEM). Small amounts of Cu in the solder affect the types of IMC phases and the amount of the IMC. The activation energies of (Cu,Ni) 6 Sn 5 and (Ni,Cu) 3 Sn 4 IMCs were used to estimate the growth kinetics of IMCs. The growth of IMCs formed in aging was very slow and temperature-dependent compared to IMCs formed in reflow because of the higher activation energies of IMCs in aging. Comparing activation energies of each IMC, growth mechanism of IMCs at electroless Ni-P/ SnAgCu solder interface will be discussed.

The focus of this study is on the role of Cu content in the dissolution kinetics of Cu in high-Sn solders during the solid/liquid reaction accompanied by interfacial intermetallic compound formation. Small additions of Cu (0.7%, 1.5%) in high-Sn solders dramatically decrease the dissolution rate of Cu at low temperatures. Sn-3.5Ag, as expected, has a dissolution rate similar to that of pure Sn. The difference in dissolution rate of Cu in various molten solders is explained in terms of the solubility limit of Cu in molten solders based on the Cu-Sn phase diagram. The correlation between the metallurgical aspects of interfacial eta(Cu6Sn5) phase formation and dissolution kinetics of Cu in molten solders leads to an understanding of the mechanism that controls the dissolution rate of Cu in molten solders

No abstract

In the last years strong efforts were made to miniaturize microelectronic systems. Chip scale packages, flip chips and multichip modules are now commonly used in a great variety of products (e. g. mobile phones, hand-held computers and chip cards). Future microelectronic applications require significantly more complex devices with increased functionality and performance. Due to added device content, chip area will also increase. Performance, multi-functionality and reliability of microelectronic systems will be limited mainly by the wiring between the subsystems (so called “wiring crisis”), causing a critical performance bottleneck for future IC generations. 3D System Integration provides a base to overcome these drawbacks. Furthermore, systems with minimum volume and weight as well as reduced power consumption can be realized for portable applications. 3D integrated systems show reduced chip areas and enable optimized partitioning, both which decrease the fabrication cost of the system. An additional benefit is the enabling of minimal interconnection lengths and the elimination of speed-limiting inter-chip interconnects. 3D concepts which take advantage of wafer level processing to avoid increasing package sizes and expensive single component assembling processes have the potential to integrate passive devices resistors, inductors and capacitors into the manufacturing system and provide full advantage for system performance.The ITRS roadmap predicts an increasing demand for systems-on-a-chip (SoC) [1]. Conventional fabrication is based on embedded technologies which are cost intensive. A new low cost fabrication approach for vertical system integration is introduced. The wafer-level 3D SoC technology, optimized to the capability for chip-to-wafer stacking has the potential to replace embedded technologies based on monolithic integration.

No abstract