3D System Integration Technologies

Abstract

In the last years strong efforts were made to miniaturize microelectronic systems. Chip scale packages, flip chips and multichip modules are now commonly used in a great variety of products (e. g. mobile phones, hand-held computers and chip cards). Future microelectronic applications require significantly more complex devices with increased functionality and performance. Due to added device content, chip area will also increase. Performance, multi-functionality and reliability of microelectronic systems will be limited mainly by the wiring between the subsystems (so called “wiring crisis”), causing a critical performance bottleneck for future IC generations. 3D System Integration provides a base to overcome these drawbacks. Furthermore, systems with minimum volume and weight as well as reduced power consumption can be realized for portable applications. 3D integrated systems show reduced chip areas and enable optimized partitioning, both which decrease the fabrication cost of the system. An additional benefit is the enabling of minimal interconnection lengths and the elimination of speed-limiting inter-chip interconnects. 3D concepts which take advantage of wafer level processing to avoid increasing package sizes and expensive single component assembling processes have the potential to integrate passive devices resistors, inductors and capacitors into the manufacturing system and provide full advantage for system performance.The ITRS roadmap predicts an increasing demand for systems-on-a-chip (SoC) [1]. Conventional fabrication is based on embedded technologies which are cost intensive. A new low cost fabrication approach for vertical system integration is introduced. The wafer-level 3D SoC technology, optimized to the capability for chip-to-wafer stacking has the potential to replace embedded technologies based on monolithic integration.

Thermal resistance measurements of interconnections for a three-dimensional (3D) chip stack

“…The measurement of the thermal conductivity of SiO 2 is left for the future study. 2 /W and those of 500μm-pitch joined sample are 209 -213 C-mm 2 /W, as summarized in Table 1. The thermal conductivity of an interconnection is derived through the comparisons with modeling, using the finite-element-method.…”

“…Three-dimensional integrated circuits (ICs) are receiving increased attention for system performance enhancements without relying on further device scaling [1][2][3]. However, because of the limited contact area and the higher circuit densities, the cooling of 3D ICs is challenging.…”

Cu-Sn low-temperature stack bonding for 3D packaging

“…Furthermore, it can improve the product integration level greatly [2]. Several bonding schemes such as metal bonding, SiO2 direct bonding [3], adhesive bonding [4], and hybrid bonding [5] have been proposed for reliable vertical interconnections in 3D integration. Both SiO2 direct bonding and adhesive bonding are simple mechanical bonds.…”

IMC bonding for 3D interconnection

“…With increasing demands for high I/O bandwidth and high performance for 3D integration, the interconnections are shrinking and reliable and robust fine-pitch interconnection technologies are needed [8,9]. Several bonding schemes such as metal bonding, SiO 2 direct bonding [10], adhesive bonding [11], and hybrid bonding [12] have been proposed for reliable vertical interconnections in 3D integration. Both SiO 2 direct bonding and adhesive bonding are simple mechanical bonds.…”

“…Therefore via formation and via filling processes are needed after the bonding process to electrically connect each stacked layer. Metal bonding techniques, such as C4 [14], low-volume solder [1,5,11], and direct Cu-to-Cu [13], are the main candidates for the micro-bumps to form electrical interconnections in 3D integration. Cu-to-Cu bonding is preferred, since Cu has superior heat conductance and low resistance.…”