No abstract

To propose an appropriate cooling solution for a threedimensional (3D) chip stack at the design phase, it is necessary to estimate the total thermal resistance of a 3D chip stack. The interconnection between stacked chips is considered as one of the thermal resistance bottleneck of a 3D chip stack, but it is not experimentally clear yet. We have previously measured the thermal conductivity of SnAg with Cu post to be 37-41W/mC by a steady state thermal resistance measurement method, using the sample which was simply composed of two Si chips and SnAg with Cu post between two Si chips. In this study, 3D stacked test chips are fabricated, which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating, and the thermal conductivity of the interconnection in actual 3D stacked structure is experimentally obtained. The temperature distributions of two 3-layer-stacked-test-chips are measured and the equivalent thermal conductivity of the interconnection is experimentally obtained to be 1.6W/mC. This value is compared with the measured thermal conductivity of SnAg with Cu post (37-41W/mC) and its adequacy is examined.

To determine an appropriate cooling solution for a 3D chip stack at the design phase, it is important to estimate the total thermal resistance of a 3D chip stack by modeling correctly. It requires the parameters in the modeling to be precise (the parameter here corresponds to the thermal conductivity of each component of a 3D chip stack) and therefore precise thermal resistance measurement of each component of a 3D chip stack is necessary. A 3D chip stack is composed of interconnections, silicon substrates, back-end-ofthe-line (BEOL), front-end-of-the-line (FEOL) and in this study, the thermal resistance of interconnections is the primary focus because interconnections are regarded as one of the thermal resistance bottlenecks of a 3D chip stack. The thermal resistances of stacked chips (each chip of 730μm thick) with the 250μm pitch (50μm diameter), 500μm pitch (50μm diameter) lead-free (SnAg) interconnections are measured and compared with the modeled results, then the thermal conductivity of SnAg interconnections is derived. The obtained the thermal conductivity of SnAg interconnections with Cu posts is 37 -41 W/mC. The dependence of the silicon effective thermal resistance on the interconnection pitch is also studied and it is experimentally proved.

No abstract

Three-dimensional (3D) chip stacks are receiving more attention for system performance enhancements, due to their higher interconnect density and shorter interconnect length. However, because of the limited contact area with a cooling method and the higher circuit density, the cooling of 3D chip stacks gets more challenging. In order to determine an appropriate cooling solution for various 3D chip stack cases at the design phase, it is important to estimate the total thermal resistance of a 3D chip stack by correct simulation. In 3D-IC 2009, the thermal resistance of interconnections is experimentally obtained because the interconnections are regarded as one of the thermal resistance bottlenecks of a 3D chip stack. In this study, 3D stacked test chips are fabricated, to determine the thermal effect of interconnections in actual 3D chip stack structure. The temperature distribution of a 3D stacked test chip is measured and the corresponding simulation model is built. The equivalent thermal conductivity of the interconnection layer is obtained to be 1.5 W/mC and it is compared with the measured thermal conductivity of SnAg with Cu posts (37 -41 W/mC).