We performed stacking experiments on Si dies using annular tungsten TSVs (Through Silicon Vias) and Cu studs with low-volume solder micro-bumps. Unlike standard 100-micron C4 (Controlled Collapse Chip Connection) solder balls, very small solder volumes (< 6 microns in height) form IMC (InterMetallic Compounds) in the junctions during the bonding or reflow processes. The two interconnect metallurgies of Cu/Ni/In and Cu/Sn joints were considered for low-volume lead-free solder micro-bumps for 3D integration. A previous study on these metallurgies [5] showed that the Cu/Sn joints form thermally stable intermetallics while in the Cu/Ni/In joints, some indium solder remains unreacted due to the presence of the Ni barriers. The shear testing on the stacked systems showed that the die stacks with Cu/Sn joints exhibit higher shear strengths than those with Cu/Ni/In joints. However the impact shock testing on the systems revealed that the die stacks with Cu/Sn joints are less resistant to mechanical shocks than the systems with Cu/Ni/In joints. This new work focuses on thermal cycle testing of the die stack systems with the Cu/Ni/In and Cu/Sn interconnections. Preliminary thermal cycle testing on the die stack systems with Cu/Ni/In joints showed that the joints are stable against thermal cycle stresses for thousands of cycles. To quickly compare the systems with two metallurgies, we mounted the Si die stacks onto organic substrates to impose additional stresses on the systems. In addition to standard DTC (Deep Thermal Cycle) tests, we also conducted a HAATS (Highly accelerated Air to Air Thermal Shock) test [23] with a short cycle time to reduce the testing time. The DTC and HAATS tests showed that the stacked systems with Cu/Ni/In joints had fewer failures and smaller increases in the electrical resistances of the joints during the tests than the systems with Cu/Sn joints.

We have prototyped a 13.3‐inch diagonal color filterless LCD illuminated with LEDs. A new color directional backlight combined with a microlens attached liquid crystal cell plate shows the feasibility of a new power efficient LCD with better color and lead‐free features.

We have developed a die-to-wafer integration technology for high yield and throughput for the formation of high bandwidth, high performance, and short-distance interconnections in three-dimensional (3D) stack applications. The results show that multiple 70-µm thick die can be successfully assembled in stacks on top of a wafer using a single bonding step, rather than by repeated sequential bonding steps. In this study, 1-die, 3-die, and 6-die stacks were assembled and the electrical resistance of link chains consisting of through-silicon-vias (TSVs), low-volume leadfree interconnects, and Cu wiring links was measured. The average resistance of the TSV including the lead-free interconnect was as low as 21 mΩ. The stacking throughput can be dramatically improved by this die-to-wafer integration technology and the contact resistance and reliability test results suggest that a reliable integration technology can be used for 3D stack applications. IntroductionSemiconductor devices have realized improvements in performance with high speed, increased functionality, low power dissipation, and low cost by continuing their remarkable miniaturization and high degree of integration per Moore's Law. However, with further miniaturization to 32 nm and smaller, problems such as increasing costs of capital investment and research and development, as well as technical problems such as increasing transistor leakage current mean that continued miniaturization at historical rates of development is becoming difficult. To address such problems, 3D integrated multiple circuits are considered to be a promising solution. This is because 3D integration technology should make it possible to improve performance by stacking chips with 32 nm features rather than simply shrinking the device dimensions.There are several different approaches for 3D integration, including die-to-die, die-to-wafer, and wafer-to-wafer. Since actual implementations have been emphasized, die-to-die approaches have taken the lead in development. Technologies in which dies are directly connected to other dies by using vertical interconnects have been proposed and several different processes for making TSVs and low-volume leadfree solder interconnects have been studied [1][2][3][4][5][6]. Each die is aligned and stacked by using high-precision flip chip bonding. Die-to-die integration provides higher flexibility and higher yield, since it's possible to sort known good die (KGD) before stacking. However, low fabrication throughput

To propose an appropriate cooling solution for a threedimensional (3D) chip stack at the design phase, it is necessary to estimate the total thermal resistance of a 3D chip stack. The interconnection between stacked chips is considered as one of the thermal resistance bottleneck of a 3D chip stack, but it is not experimentally clear yet. We have previously measured the thermal conductivity of SnAg with Cu post to be 37-41W/mC by a steady state thermal resistance measurement method, using the sample which was simply composed of two Si chips and SnAg with Cu post between two Si chips. In this study, 3D stacked test chips are fabricated, which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating, and the thermal conductivity of the interconnection in actual 3D stacked structure is experimentally obtained. The temperature distributions of two 3-layer-stacked-test-chips are measured and the equivalent thermal conductivity of the interconnection is experimentally obtained to be 1.6W/mC. This value is compared with the measured thermal conductivity of SnAg with Cu post (37-41W/mC) and its adequacy is examined.

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