Die-to-Wafer 3D Integration Technology for High Yield and Throughput

J. Micromech. Microeng.

et al. 2011

We developed a vacuum underfill technology for 3D chip stacks and for flip chips in high performance system integration. We fabricated a 3D prototype chip stack using the vacuum underfill technology to apply the adhesive. The underfill was injected into each 6 µm gaps in a 3-layer chip stack and no voids were detected in acoustic microscopy images. Electrical tests and thermal reliability tests were used to measure the resistance of the vertical interconnections and the impact of the underfill. The results showed there was minimal difference in the average interconnection resistance of the chip stack with and without underfill.

Section: Methodsmentioning

confidence: 99%

Development of vacuum underfill technology for a 3D chip stack

Sakuma

Kohara

J. Micromech. Microeng.

et al. 2011

“…The TSV (Through Silicon Via) pitch is 200Pm and its diameter is 80Pm. Three chips are bonded simultaneously in a bonding process described in the ref [19,20]. A bonding tool heats the chips above the melting temperature of the low-volume leadfree solder bumps and applies pressure to the chip stack, and a three-layer chip stack is fabricated (Fig.3).…”

Section: Structure Of a 3d Stacked Test Chipmentioning

confidence: 99%

Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack

Matsumoto

Ibaraki

2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium

et al. 2011

Self Cite

To propose an appropriate cooling solution for a threedimensional (3D) chip stack at the design phase, it is necessary to estimate the total thermal resistance of a 3D chip stack. The interconnection between stacked chips is considered as one of the thermal resistance bottleneck of a 3D chip stack, but it is not experimentally clear yet. We have previously measured the thermal conductivity of SnAg with Cu post to be 37-41W/mC by a steady state thermal resistance measurement method, using the sample which was simply composed of two Si chips and SnAg with Cu post between two Si chips. In this study, 3D stacked test chips are fabricated, which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating, and the thermal conductivity of the interconnection in actual 3D stacked structure is experimentally obtained. The temperature distributions of two 3-layer-stacked-test-chips are measured and the equivalent thermal conductivity of the interconnection is experimentally obtained to be 1.6W/mC. This value is compared with the measured thermal conductivity of SnAg with Cu post (37-41W/mC) and its adequacy is examined.

“…The diameter of each bump is 100 m and the pitch size is 200 m. The TSV process flow has been described elsewhere [16][17][18] and is only summarized here. The annular vias are formed by deep RIE, after which they are insulated by thermal oxidation.…”

Section: Test Vehicle Fabrication Processmentioning

confidence: 99%

IMC bonding for 3D interconnection

Sakuma

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

Kohara

et al. 2010

We performed stacking experiments on Si dies using annular tungsten TSVs (Through Silicon Vias) and Cu studs with low-volume solder micro-bumps. Unlike standard 100-micron C4 (Controlled Collapse Chip Connection) solder balls, very small solder volumes (< 6 microns in height) form IMC (InterMetallic Compounds) in the junctions during the bonding or reflow processes. The two interconnect metallurgies of Cu/Ni/In and Cu/Sn joints were considered for low-volume lead-free solder micro-bumps for 3D integration. A previous study on these metallurgies [5] showed that the Cu/Sn joints form thermally stable intermetallics while in the Cu/Ni/In joints, some indium solder remains unreacted due to the presence of the Ni barriers. The shear testing on the stacked systems showed that the die stacks with Cu/Sn joints exhibit higher shear strengths than those with Cu/Ni/In joints. However the impact shock testing on the systems revealed that the die stacks with Cu/Sn joints are less resistant to mechanical shocks than the systems with Cu/Ni/In joints. This new work focuses on thermal cycle testing of the die stack systems with the Cu/Ni/In and Cu/Sn interconnections. Preliminary thermal cycle testing on the die stack systems with Cu/Ni/In joints showed that the joints are stable against thermal cycle stresses for thousands of cycles. To quickly compare the systems with two metallurgies, we mounted the Si die stacks onto organic substrates to impose additional stresses on the systems. In addition to standard DTC (Deep Thermal Cycle) tests, we also conducted a HAATS (Highly accelerated Air to Air Thermal Shock) test [23] with a short cycle time to reduce the testing time. The DTC and HAATS tests showed that the stacked systems with Cu/Ni/In joints had fewer failures and smaller increases in the electrical resistances of the joints during the tests than the systems with Cu/Sn joints.